ARM: vmlinux.lds.S: do not hardcode cacheline size as 32 bytes

The linker script assumes a cacheline size of 32 bytes when aligning
the .data..cacheline_aligned and .data..percpu sections.

This patch updates the script to use L1_CACHE_BYTES, which should be set
to 64 on platforms that require it.

Signed-off-by: Will Deacon <will.deacon@xxxxxxx>
ARM: vmlinux.lds.S: align the exception fixup table to a 4-byte boundary

The exception fixup table is currently aligned to a 32-byte boundary.
Whilst this won't cause any problems, the exception_table_entry
structures contain only a pair of unsigned longs, so 4-byte alignment
is all that is required.

Cc: Nicolas Pitre <nico@xxxxxxxxxxx>
Signed-off-by: Will Deacon <will.deacon@xxxxxxx>