target-arm: aarch64: add support for logical (shifted register)

this adds support for the instructions described in:
C3.5.10 Logical (shifted register)

Support includes a reworking of flags, and a way to read the
registers in copy mode that also zero extends on 32bit access.

Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>

from Alexander Graf <agraf@suse.de> aarch64 series 14/60