Preparing system or1200-generic for Verilator. Introducing the JtagServer sysc component.
orpsoc_top with jtag i/f
Merge branch 'master' of https://github.com/jjts/orpsoc-cores
JtagServerSC.cpp JtagServerSC.h OrpsocMain.cpp/h orpsoc_top.v
       deleted:    systems/or1200-generic/bench/verilator/JtagServer.cpp
       deleted:    systems/or1200-generic/bench/verilator/JtagServer.h
       modified:   systems/or1200-generic/bench/verilator/OrpsocMain.cpp
       modified:   systems/or1200-generic/bench/verilator/OrpsocMain.h
       modified:   systems/or1200-generic/bench/verilog/orpsoc_top.v
       modified:   systems/or1200-generic/or1200-generic.core
JtagServerSC.cpp
OrpsocMain.cpp
orpsoc_top.v

Improvements to the above files but 10-Hellos exemple still does not print OK.
Processor is affected by the presence of the debug module.... ? Plan:
Investigate the print process.... (no UART present)
Merge remote-tracking branch 'jose/master'
merge