v4l: xilinx: Add Xilinx Video IP core

Xilinx Zynq platforms have no hardwired camera interface. Users create
camera pipelines in the FPGA fabric to suit their particular needs, by
instantiating video IP cores from a large library.

The Xilinx Video IP core is a framework that models a video pipeline
described in the device tree and expose the pipeline to userspace
through the media controller and V4L2 APIs.

Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
v4l: xilinx: Add Test Pattern Generator driver

The TPG generates multiple static or dynamic test patterns. The driver
currently hardcodes the pattern to the moving box pattern.

Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
v4l: xilinx: Add Video Remapper driver

The remapper is a non-configurable IP core that remaps the video bus
data lines. The driver includes a list of mappings and exposes them
through the get and set media bus format operations.

Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>