added testbench, 1st commit
updated top level aes module (rtl)
working dpi interface
Merge branch 'dechhin' of github.com:ams2378/aes_core into adil
compiling branch adil
stash
updated codes..few issues exists on receiving ciphertext from C
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changed simulation to get correct exchange of data from c to sv and vicecersa
working argument passing
WOKRING arg passing between SV and C model
edit bench
constraint
update soft
update soft
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