Perf: Restore correct CPU's PMU counters after power collpase

Since the L1CC PMU's are per CPU, the variable to detect if a CPU
came out of powercollapse also needs to be a per CPU variable. This
ensures that we reset and restore the correct CPU's PMU counters.

Change-Id: I02273df2eff9f6d88d68f46a7752c107b290a8ef
Signed-off-by: Ashwin Chaugule <ashwinc@codeaurora.org>
Perf: Make L1 PMU IRQ name target independent

Remove target name from IRQ string, since the percpu IRQ API
is shared with all Qcomm targets.

Change-Id: Id0e7d9267654b373e9360806900259e00bf5a0ab
Signed-off-by: Ashwin Chaugule <ashwinc@codeaurora.org>
Perf: Change IRQ functions for CPU variants

Unicore targets can't use the percpu IRQ API,
so fallback to the generic versions of the functions
at init.

Change-Id: Id3db611fe4a7e0dcfbeb2f3ae08a5f7189132034
Signed-off-by: Ashwin Chaugule <ashwinc@codeaurora.org>
Perf: Add generic IRQ handlers for ARMv7 PMU's

For ARMV7 based PMU's implemented outside Qcomm, default
to the generic IRQ handlers to maintain original behavior.

Change-Id: Ic65379104cc708460f2f84c00ea86c1e284bbd29
Signed-off-by: Ashwin Chaugule <ashwinc@codeaurora.org>
Perf: Let platforms decide IRQ request methods.

This is in preparation for adding support for the unicore A5
and dualcore A5, both of which have the same MIDR value.

Instead of adding extra parsing to the ARM generic perf_event file,
this patch moves it to the 'mach' directory where targets types
can be detected in an implementation specific manner.

The default behavior is maintained for all other ARM targets.

Change-Id: I041937273dbbd0fa4c602cf89a2e0fee7f73342b
Signed-off-by: Ashwin Chaugule <ashwinc@codeaurora.org>
msm: Perf: Differentiate between L1 and L2 PMU IRQs

The L2 perf code shares some resource reservation functions
with the L1 perf code. In these functions, use defaults
only if they're not defined for the L1 and L2.

Change-Id: I5a390aa0085694466800db78b51837556aa12cdd
Signed-off-by: Ashwin Chaugule <ashwinc@codeaurora.org>
Perf: Assign proper routine to free IRQ

If the platform descriptor does not provide
its own free_irq function, default to the fallback
version.

Change-Id: I185186bf68b79e2dbfba77b0de66eb4daaf32fb8
Signed-off-by: Ashwin Chaugule <ashwinc@codeaurora.org>
msm: perf: Relax Column exclusion checks for L2CC events

Identical L2CC events with the same register, code and group
can be set up with individual origin filters. The hardware
restricts counting only for identical register and group settings
but a different value for the event code.

Detect such identical events and let them pass the constraint
checks.

Change-Id: I609defb5c5b070b1007b2e7db9e2d8315d2ba1d7
Signed-off-by: Ashwin Chaugule <ashwinc@codeaurora.org>
msm: perf: add debug patch logging framework

Provide a mechanism to track which msm perf patches
are present in a kernel. Some kernel branches do
not include all patches which causes problems trying
to debug perf issues. This framework provides a way
to keep track of which patches have been included
in a build.

Change-Id: Ib8ef311454564c4609d94decd93e039c80104275
Signed-off-by: Neil Leeder <nleeder@codeaurora.org>
Perf: Restore counter after powercollapse for generic ARM PMU's

The MSM SoC's which have ARM's CPU's can power collapse. Ensure
the CPU side PMU's correctly restore the counters after coming
out of power collapse.

Change-Id: I544a1dd8ced26f726ba115d14867d9e34c2a7944
Signed-off-by: Ashwin Chaugule <ashwinc@codeaurora.org>
media: dvb: mpq: Limit number of TS packets on secure demux input

Limit number of TS packets available to secure demux for processing
in any single processing session. This is done in order to prevent
large input buffer that require a long processing time and may cause
latency and overflow situations.
The limit can be fine-tuned as it is a module parameter.

Change-Id: I36f007da1b8152be27885ba4674bf42e6eb86ffa
Signed-off-by: Gilad Broner <gbroner@codeaurora.org>
msm_fb: display: Configure solidfill color to black

The solidfill color was getting reset to to default state to white.
Correctly reseting to black by default.

Crs-Fixed: 453600
Change-Id: I203ce61867d009509bf6acd01169f1fb0b223652
Signed-off-by: Siddhartha Agrawal <agrawals@codeaurora.org>
wireless: add VHT (802.11ac) definitions

Add the VHT definitions to be used by drivers supporting it.

Change-Id: Ia301cf72940cef19767f4f485a09c9afc12ae514
CRs-fixed: 452921

Signed-off-by: Mahesh Palivela <maheshp@posedge.com>
Signed-off-by: Johannes Berg <johannes.berg@intel.com>
cfg80211: allow advertising VHT capabilities

Allow drivers to advertise their VHT capabilities
and export them to userspace via nl80211.

Change-Id: I2d2825a09dfddccca1bd3edacd7fc382d765bea5
CRs-fixed: 452921

Signed-off-by: Mahesh Palivela <maheshp@posedge.com>
Signed-off-by: Johannes Berg <johannes.berg@intel.com>
mac80211: include VHT capability IE in probe requests

Insert the VHT capability IE into probe requests.

Change-Id: I75620090969b46701f1c760baf9c6559a4a1ac2c
CRs-fixed: 452921

Signed-off-by: Mahesh Palivela <maheshp@posedge.com>
Signed-off-by: Johannes Berg <johannes.berg@intel.com>
hwmon: pm8xxx-adc: Vote for a PMIC clock buffer.:

Incorrect PMIC_THERM/XO_THERM readings are seen when
the XO clock is disabled.

The internal PMIC therm relies on the PMIC band gap
reference which in turn is enabled when any of the
PMIC clock buffers are enabled. The XO_THERM relies
on the VREF_XO as its reference source which gets
enabled when any of the PMIC clock buffers are
switched on. Therefore vote for a clock buffer when
a PMIC_THERM/XO_THERM is requested.

CRs-Fixed: 392602
Signed-off-by: Siddartha Mohanadoss <smohanad@codeaurora.org>
(cherry picked from commit f9dfe1b7b70b634422fbbbf65756aa997536bd33)

Change-Id: I09e132dbc4e635b96cd08ece245a766d68ed27b4
Signed-off-by: Sridhar Gujje <sgujje@codeaurora.org>

Conflicts:

	drivers/hwmon/pm8xxx-adc.c

Signed-off-by: Sridhar Gujje <sgujje@codeaurora.org>
Signed-off-by: Sivasri Kumar Vanka <sivasri@codeaurora.org>
(cherry picked from commit 8ab75c713cef66317f9507b35cc08a5d7b49ae44)

Conflicts:

	drivers/hwmon/pm8xxx-adc.c

Signed-off-by: Sridhar Gujje <sgujje@codeaurora.org>
Perf: Toggle PMU IRQ when CPU's are hotplugged

When a CPU is hotplugged out while a perf session
is active, disarm the IRQ when the CPU is preparing
to die. This ensures that perf doesn't lock up when
it tries to free the irq of a hotplugged CPU.
Similarly, when a CPU comes online during a perf session
enable the IRQ so that perf doesn't try to disable
an unarmed IRQ when it finishes.

Change-Id: Ic4e412e5f1effae0db34a3e4b5e7e5c65faed2a0
Signed-off-by: Ashwin Chaugule <ashwinc@codeaurora.org>
Perf: Correct irq for CPU hotplug detection

The platform data was requesting the wrong number,
it should request the first perf irq item.

Change-Id: I4a25b4704ed9e76172c6b0d4ca4b28a3286ab2ad
Signed-off-by: Neil Leeder <nleeder@codeaurora.org>
android/lowmemorykiller: Ignore tasks with freed mm

A killed task can stay in the task list long after its
memory has been returned to the system, therefore
ignore any tasks whose mm struct has been freed.

Change-Id: I76394b203b4ab2312437c839976f0ecb7b6dde4e
CRs-fixed: 450383
Signed-off-by: Liam Mark <lmark@codeaurora.org>
msm: audio: qdsp6v2: Add NULL checking for input parameters

Add checking for NULL. Two parameters shouldn't be NULL.

Change-Id: Ied9e9e6238f6498305844bf3a08370c7cf751fc7
Signed-off-by: Fred Oh <fred@codeaurora.org>