[OMAP5][DPLL] Fix show dpll M2 divider

The [1/2] divider located after the M2 post-divider is not valid when
the CM_CLKSEL_DPLL_MPU[22] DCC_EN bit is set (applies only to DPLL_MPU
when a frequency higher than 1.4 GHz is needed).

Therefore, when DCC is enable, it should print (x1) instead of (x2)
next to the M2 post-divider.

Acked-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Jin Zheng <j-zheng@ti.com>