Changed usb2_top interface to remove the data inout signal in favor of separate in/out/oe signals. This permits simpler control of signals at strapping (USB PHY reset) time.
Updated RS232 target project to reflect above change.
Removed local io_seg7.v from RS232 target project. The file was moved to common/.
Main board FPGA diagnostic project. At present, it runs from the Si5351C-B clocks and brings up the ULPI interface to the extent that the board will enumerate with a host.
A program.sh example script is provided for programming the FPGA over JTAG via a Dangerous Prototypes Bus Blaster.