hdl: re-indent design top file.
hdl: re-indent, update project to ise 13.3
hdl: Add hdlmake Manifest files.
hdl: Remove outdated .ise project file.
hdl: Continue clean-up, move to numeric_std library.
hdl: Continue clean-up, add proper sync for front panel inputs (to be connected).
Merge branches 'master' and 'mcattin_dev' of github.com:mcattin/cvora into mcattin_dev
hdl: Work on the registers. Renaming in progress.

- mode is now 4 bits
- no default mode with jumpers
- all fp inputs sync'ed with gc_sync_ffs
- data from interface controller sampled on rising edge of sys_clk
hdl: Continue clean-up.

- simpler pps counter
- gc_extend_pulse for LED monostable
- generic up/down counter module
- clean sci decoder (was P2Serial)
- add cvrob decoder (from Damien Perrelet BE/RF)
- more renaming on top level
hdl: Work in progress. Re-writting serial decoders.
hdl: Work on rtm serial data manager.
hdl: Work on ram manager.
hdl: Clean-up, version with new 2x16 and cvorb modes. To be tested.
hdl: Rename package, use numeric_std instead of std_logic_unsigned and std_logic_arith.
hdl: Rename files, rename ports and signals on top entity, use extend_pulse from general-cores for dac load pulse generation.
hdl: Add script to generate .xsvf file from .bit
hdl: Remove unused files.
hdl: Rename .bit file in xsvf geenration script.
hdl: Add makefile for xsvf generation, add ise project and reports.
doc: Add notes on gateware test procedure.