Add a vg_alignof macro

Note that this macro behaves slightly differently for some types
from the gcc __alignof__ and from the equivalent (new) standardised
alignof. 

vg_alignof macro is needed for the "perm_malloc" callers (next commit)
to determine the alignment of small blocks, but might be useful
for other purposes => placed in libvex_basictypes.h, close to offsetof.



git-svn-id: svn://svn.valgrind.org/vex/trunk@2643 8f6e269a-dfd6-0310-a8e1-e2731360e62c
s390: Fix a type mixup spotted by IBM's BEAM checker.


git-svn-id: svn://svn.valgrind.org/vex/trunk@2644 8f6e269a-dfd6-0310-a8e1-e2731360e62c
Improve the tree builder in IR optimisation. Allow load expressions to be
moved past Put/I statements and dirty helpers, when it is safe to do so.
It is safe, when the statement does not require exact memory exceptions.
New functions stmt_modifies_guest_state and dirty_helper_puts have been
added to determine the side effect on the guest state.
This optimisation enables the use of  memory-to-memory insns on
architectures that have those.


git-svn-id: svn://svn.valgrind.org/vex/trunk@2645 8f6e269a-dfd6-0310-a8e1-e2731360e62c
Remove a bit of dead code, spotted by Florian using Coverity.


git-svn-id: svn://svn.valgrind.org/vex/trunk@2646 8f6e269a-dfd6-0310-a8e1-e2731360e62c
Fold out an expression which is always False.  Spotted by Florian using Coverity.


git-svn-id: svn://svn.valgrind.org/vex/trunk@2647 8f6e269a-dfd6-0310-a8e1-e2731360e62c
mips: fix for mips-disassembler when branch is at block_size-2 position

Check if the last instruction in the block is a branch or jump instruction
should happen only if the disassembler was not already stopped.
Incorrect conditional led to a boundary case in which jumps/branches were not
executed when placed on "max_insns - 2" position in the block.
none/tests/mips32/block_size test will be added to Valgrind to describe the case
and check for regressions in future.


git-svn-id: svn://svn.valgrind.org/vex/trunk@2648 8f6e269a-dfd6-0310-a8e1-e2731360e62c
mips: fixing issues spotted by a static code analysis tool

Florian ran a static code analysis tool and found the issues.
Cleaning out old cruft now.


git-svn-id: svn://svn.valgrind.org/vex/trunk@2649 8f6e269a-dfd6-0310-a8e1-e2731360e62c
 The 32-bit DFP value is stored in a 64-bit register in
 ppc. The D32 to D64 and D64 to D32 definitions for the
 Iop type was specified in VEX/priv/ir_defs.c, function
 typeOfPrimop() as:

   case Iop_D32toD64:
      UNARY(Ity_64, Ity_D64);
   case Iop_D64toD32:
      BINARY(ity_RMode, Ity_D64, Ity_D64);

since the values resided in a 64-bit register. As part of the s390 DFP support
the definitions were changed to:

   case Iop_D32toD64:
      UNARY(Ity_32, Ity_D64);
   case Iop_D64toD32:
      BINARY(ity_RMode, Ity_D64, Ity_D32);

to reflect what they really should be. However, this broke the ppc
implementation. Valgrind would fail and report a mismatch on the types as the
ppc code was using a D64 instead of a D32.

This patch adds support for fetching and storing the Dfp32 operand as a 32-bit
value.  The support includes adding the functions iselDfp32Expr() and
iselDfp32Expr_wrk() and additional code to support the DFP32 bit iops.

This patch is for Bugzilla 312620.


git-svn-id: svn://svn.valgrind.org/vex/trunk@2650 8f6e269a-dfd6-0310-a8e1-e2731360e62c
s390: Remove unreachable break statements.
Spotted and fixed by Maran Pakkirisamy (maranp@linux.vnet.ibm.com).


git-svn-id: svn://svn.valgrind.org/vex/trunk@2651 8f6e269a-dfd6-0310-a8e1-e2731360e62c
Fix implementation of the DFP integer operands.

The implementation of integer operands doesn't really match the documentation
for the Iop. Take for example Iop_ExtractExpD64. It is documented as
D64 -> I64 but the implementation of the UNARY is defined as
UNARY(Ity_D64, Ity_D64). The result is an integer that is stored in an integer
format in a floating point register. On the IBM s390 however, the architecture
stores the integer value in a general purpose register (GPR) not a floating
point register. This issue exists with the implementation of 11 Iops where the
PPC implementation has either a source or destination whose value is an integer
but the value is stored in a floating point register in an integer format. After
reviewing the PPC implementation with the s390 developer, it was agreed the
cleanest way to fix this is to change the PPC implementation. The BINOP will be
changed to be consistent with the Iop description. This means the PPC
instruction implementation of the PPC instruction in guest_ppc_toIR.c will need
to reinterpret integer source operands as integers which will move the value
from a floating point register to an integer register before calling binop().
The underlying PPC implementation of the unop() for the specific Iop will also
need to change to move the value from the integer register back to the floating
point register so the native instruction can be issued with the integer value
in a floating point register. It was decided that making the changed in PPC,
rather then having the s390 reinterpret integers as DFP and then move the value
back to an integer register, was preferable as it makes the implementation of
the unop(), binops(), triop() consistent with the definition of the Iop.

This patch also includes the needed changes for the vbit tester.  The Iop
definitions in memcheck/tests/vbit-test/util.c had to be updated to be consitent
with the changes in the Iops as documented below.  Also, the function mkLazy3()
in memcheck/mc_translate.c had to be updated to handle the I32 x I8 x I64 -> I64
and I32 x I8 x I128 -> I128 cases.

The specific list of changes are as follows:

Iop name in pub/libvex_ir.h
   documented type
     type of UNARY/BINARY/TERNARY in priv/ir_defs.c
-------------------------------------------------------

Iop_ExtractExpD64
   D64 -> I64
      UNARY(Ity_D64, Ity_D64); (current)
      UNARY(Ity_D64, Ity_I64); (fix)
 

Iop_ExtractExpD128
   D128 -> I64
       UNARY(Ity_D128, Ity_D64); (current)
       UNARY(Ity_D128, Ity_I64); (fix)

Iop_InsertExpD64
   I64 x I64 -> D64
   I64 x D64 -> D64 (fix definition)
       BINARY(Ity_D64,Ity_D64, Ity_D64); (current)
       BINARY(Ity_I64,Ity_D64, Ity_D64); (fix)

Iop_InsertExpD128
    I64 x I128 -> D128
    I64 x D128 -> D128 (fix definition)
        BINARY(Ity_D64,Ity_D128, Ity_D128); (current)
        BINARY(Ity_I64,Ity_D128, Ity_D128); (fix)

Iop_I64StoD128
    I64S -> D128
        UNARY(Ity_D64, Ity_D128); (current)
        UNARY(Ity_I64, Ity_D128); (fix)

Iop_D64toI64S
    IRRoundingModeDFP(I32) x D64 -> I64
        BINARY(ity_RMode, Ity_D64, Ity_D64) (current)
        BINARY(ity_RMode, Ity_D64, Ity_I64) (fix)

Iop_D128toI64S
    IRRoundingModeDFP(I32) x D128 -> I64
        BINARY(ity_RMode, Ity_D128, Ity_D64); (current)
        BINARY(ity_RMode, Ity_D128, Ity_I64); (fix)

Iop_I64StoD64
    IRRoundingModeDFP(I32) x I64 -> D64
        BINARY(ity_RMode, Ity_D64, Ity_D64); (current)
        BINARY(ity_RMode, Ity_I64, Ity_D64); (fix)

Iop_SignificanceRoundD64
    IRRoundingModeDFP(I32) x I8 x D64 -> D64
        TERNARY(ity_RMode,Ity_D64,Ity_D64, Ity_D64); (current)
        TERNARY(ity_RMode,Ity_I8,Ity_D64, Ity_D64); (fix)

Iop_SignificanceRoundD128
    IRRoundingModeDFP(I32) x I8 x D128 -> D128
         TERNARY(ity_RMode,Ity_D128,Ity_D128, Ity_D128); (current)
         TERNARY(ity_RMode,Ity_I8,Ity_D128, Ity_D128); (fix)

The patch is for bugzilla 311100

git-svn-id: svn://svn.valgrind.org/vex/trunk@2652 8f6e269a-dfd6-0310-a8e1-e2731360e62c
Unreachable default case should vassert.


git-svn-id: svn://svn.valgrind.org/vex/trunk@2653 8f6e269a-dfd6-0310-a8e1-e2731360e62c
Fix HReg <--> Uint mixup.  iregNo returns an integer not a HReg.


git-svn-id: svn://svn.valgrind.org/vex/trunk@2654 8f6e269a-dfd6-0310-a8e1-e2731360e62c
Fix HReg <--> integer mixup. vreg2ireg returns an HReg not an integer.


git-svn-id: svn://svn.valgrind.org/vex/trunk@2655 8f6e269a-dfd6-0310-a8e1-e2731360e62c
Fix some HReg/UInt mixups spotted by Florian.


git-svn-id: svn://svn.valgrind.org/vex/trunk@2656 8f6e269a-dfd6-0310-a8e1-e2731360e62c
s390: Fix HReg <--> UInt mixups.


git-svn-id: svn://svn.valgrind.org/vex/trunk@2657 8f6e269a-dfd6-0310-a8e1-e2731360e62c
Fix HReg <--> UInt mixup.
vreg is a HReg, so we should not assign a hregNumber() to it.
Introduce and use vregno instead.


git-svn-id: svn://svn.valgrind.org/vex/trunk@2658 8f6e269a-dfd6-0310-a8e1-e2731360e62c
Remove two unused variables that sneaked in in r2657.


git-svn-id: svn://svn.valgrind.org/vex/trunk@2659 8f6e269a-dfd6-0310-a8e1-e2731360e62c
Fix some HReg/UInt mixups, spotted by Florian.


git-svn-id: svn://svn.valgrind.org/vex/trunk@2660 8f6e269a-dfd6-0310-a8e1-e2731360e62c
Annotate ARMNImm_to_Imm64 with fallthrough markers following
verification against the table in host_arm_defs.h, "Neon Immediate
operand".  A particularly nasty piece of code.



git-svn-id: svn://svn.valgrind.org/vex/trunk@2661 8f6e269a-dfd6-0310-a8e1-e2731360e62c
Changes to make this usable for ARM/Thumb.


git-svn-id: svn://svn.valgrind.org/vex/trunk@2662 8f6e269a-dfd6-0310-a8e1-e2731360e62c