sim: add a simple IRQ controller.

This is a simple IRQ controller that at the moment just supports test
IRQ's and raising an IRQ to the CPU.
sim: implement interrupt support in the CPU core.
rtl: add a simple IRQ controller.

This is a basic interrupt controller supporting 32 interrupt sources.
Currently the interrupts can only be raised by register accesses
directly to the controller for testing.
keynsham: instantiate the IRQ controller.
tests: make sure that interrupts are disabled inside exceptions handlers.
rtl: replace counter from fetch stopping with pipeline busy flag.

Rather than waiting for 5 cycles, just wait until the pipeline is empty.
That's often quicker and simplifies the logic.  We can also reuse this
for hardware interrupts.
rtl: implement interrupts.

Interrupts are level triggered from outside of the core and
enabled/disabled with the I bit in the PSR.