[SystemZ] Don't use LOAD and STORE REVERSED for volatile accesses

Unlike most -- hopefully "all other", but I'm still checking -- memory
instructions we support, LOAD REVERSED and STORE REVERSED may access
the memory location several times.  This means that they are not suitable
for volatile loads and stores.

This patch is a prerequisite for better atomic load and store support.
The same principle applies there: almost all memory instructions we
support are inherently atomic ("block concurrent"), but LOAD REVERSED
and STORE REVERSED are exceptions.

Other instructions continue to allow volatile operands.  I will add
positive "allows volatile" tests at the same time as the "allows atomic
load or store" tests.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183002 91177308-0d34-0410-b5e6-96231b3b80d8
ARM: fix VEXT encoding corner case

The disassembly of VEXT instructions was too lax in the bits checked. This
fixes the case where the instruction affects Q-registers but a misaligned lane
was specified (should be UNDEFINED).

Patch by Amaury de la Vieuville

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183003 91177308-0d34-0410-b5e6-96231b3b80d8
Simplify multiplications by vectors whose elements are powers of 2.

Patch by Andrea Di Biagio.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183005 91177308-0d34-0410-b5e6-96231b3b80d8
ARM: add fstmx and fldmx instructions for assembly

These instructions are deprecated oddities, but we still need to be able to
disassemble (and reassemble) them if and when they're encountered.

Patch by Amaury de la Vieuville.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183011 91177308-0d34-0410-b5e6-96231b3b80d8
ARM: permit upper-case BE/LE on setend instruction

Patch by Amaury de la Vieuville.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183012 91177308-0d34-0410-b5e6-96231b3b80d8
Remove useless code from transitioning to new EH scheme

Removes all uses of the variable UsesNewEH. Simply return false in case that no
resume instructions were found.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183016 91177308-0d34-0410-b5e6-96231b3b80d8
Unit test for SCEV fix r182989, PR16130.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183017 91177308-0d34-0410-b5e6-96231b3b80d8
Add a way to define the bit range covered by a SubRegIndex.

NOTE: If this broke your out-of-tree backend, in *RegisterInfo.td, change
the instances of SubRegIndex that have a comps template arg to use the
ComposedSubRegIndex class instead.

In TableGen land, this adds Size and Offset attributes to SubRegIndex,
and the ComposedSubRegIndex class, for which the Size and Offset are
computed by TableGen. This also adds an accessor in MCRegisterInfo, and
Size/Offsets for the X86 and ARM subreg indices.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183020 91177308-0d34-0410-b5e6-96231b3b80d8
Modify how the formulae are rated in Loop Strength Reduce.
Namely, check if the target allows to fold more that one register in the
addressing mode and if yes, adjust the cost accordingly.

Prior to this commit, reg1 + scale * reg2 accesses were artificially preferred
to reg1 + reg2 accesses. Indeed, the cost model wrongly assumed that reg1 + reg2
needs a temporary register for the computation, whereas it was correctly
estimated for reg1 + scale * reg2.

<rdar://problem/13973908>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183021 91177308-0d34-0410-b5e6-96231b3b80d8
[APFloat] Added a unittest for APFloat::getZero.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183028 91177308-0d34-0410-b5e6-96231b3b80d8
NVPTX: Don't even create a regalloc if we're not going to use it.

Fixes a leak found by valgrind.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183031 91177308-0d34-0410-b5e6-96231b3b80d8
LoopVectorize: PHIs with only outside users should prevent vectorization

We check that instructions in the loop don't have outside users (except if
they are reduction values). Unfortunately, we skipped this check for
if-convertable PHIs.

Fixes PR16184.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183035 91177308-0d34-0410-b5e6-96231b3b80d8
Don't allocate temporary string for section data.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183040 91177308-0d34-0410-b5e6-96231b3b80d8
Remove union to fix build in c++03.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183041 91177308-0d34-0410-b5e6-96231b3b80d8
Rename COFFYaml.h to COFFYAML.h for consistency.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183042 91177308-0d34-0410-b5e6-96231b3b80d8
Use just a ArrayRef<uint8_t> to store both hex string and binary data.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183043 91177308-0d34-0410-b5e6-96231b3b80d8
Loop Strength Reduce: Scaling factor cost.

Account for the cost of scaling factor in Loop Strength Reduce when rating the
formulae. This uses a target hook.

The default implementation of the hook is: if the addressing mode is legal, the
scaling factor is free.

<rdar://problem/13806271>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183045 91177308-0d34-0410-b5e6-96231b3b80d8
LoopVectorize: Change API call to get the backedge taken count

Use ScalarEvolution's getBackedgeTakenCount API instead of getExitCount since
that is really what we want to know. Using the more specific getExitCount was
safe because we made sure that there is only one exiting block.

No functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183047 91177308-0d34-0410-b5e6-96231b3b80d8
Move "unsigned char" -> "uint8_t".

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183051 91177308-0d34-0410-b5e6-96231b3b80d8
Fix comment.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183052 91177308-0d34-0410-b5e6-96231b3b80d8