Moved original verilog implementation of logic to another folder.

rewrite of lab two used .BDF top-level file and Altera defined logic primitives. Verilog description is no longer needed but I just can't throw it out!.
First draft of comparator module and test bench.
Table formatting fix for IEEEtran class conflict with sub caption package

changed from subcaption to subfig package. [caption=false,font=footnotesize] option for subfig recommended by Michael Shell.
added footnote to explain "deterministic" systems from scholarpedia.

changed usage of subcaption package figure to use the new form for subfig .