rtl/fetch: rework the instruction fetch logic.

The old logic didn't cope when the fetch latency was greater than a
single cycle so would not work with SDRAM accesses or cache misses once
that is implemented.
bootrom: include the build ID + date.

This makes it easier to make sure that the hardware/sim is running the
version that we actually expect.
sim: boot with the onchip bootrom.

Include the bootrom so the build ID + date can be queried like the rtl
sim and FPGA.
debugger: report CPU BuildID + date on connect.
bootrom: pad to 512 bytes.

256 bytes is a little small for a reasonable bootloader.
fpga: generate the bootrom at build time.