Revert "genlib/record/connect: add match_by_position"

This reverts commit df1ed32765510421fee07a8d5ff29afa9ce7c7c5.
genlib/record: match_by_position -> connect_flat
fhdl/tools/_TargetLister: do not include array keys in targets
bus/asmi: port sharing support
setup.py: update required Python version
bus/csr/SRAM: support init
bus/wishbone/SRAM: support init and read_only
New migen.fhdl.std to simplify imports + len->flen
Make memory ports part of specials

This is needed to handle cases where a single memory has ports
in two different modules, and one of these modules is subject
to clock domain remapping. The clock domain of the port in that
module only must be remapped.
bitreverse: fhdl/tools -> genlib/misc
bus/csr/SRAM: better handling of writes to memories larger than the CSR width
genlib/misc: fix import
csr/sram: fix page_bits computation
csr/sram: fix reads on high addresses when word_bits != 0
bus/lasmi: interface definition and crossbar (untested)
examples/sim: rename abstract_transactions to abstract_transactions_wb, use new APIs, remove ASMI
bus/lasmibus: add target and initiator
bus/lasmibus: bugfixes
examples/sim: add LASMI demo
bus: Wishbone -> LASMI bridge (untested)