FPGA: The second receive channel has been made fully independent.

Some registries require changes in HOST code.
FPGA: The second transmit channel was added.

Some registries require changes in HOST code.
FPGA: Control logic for dual channel SRAM FIFO was fixed.
ZPU: Memory map has been changed according dual channel implementation.
HOST: Memory map has been changed according dual channel implementation.
ZPU: Add support for the second UDP Tx stream to ZPU and to fw_common.h.