We are now in 3.4 land. We don't need the 3.3 releaese notes in ToT anymore.

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[llvm-symbolizer] Avoid calling slow getSymbolSize for Mach-O files. Assume that symbols with zero size are in fact large enough.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183213 91177308-0d34-0410-b5e6-96231b3b80d8
Test commit for user vmedic, to verify commit access. One line of comment is added to MipsAsmParser.cpp.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183215 91177308-0d34-0410-b5e6-96231b3b80d8
Preserve const correctness.

GCC complains about casting away const.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183216 91177308-0d34-0410-b5e6-96231b3b80d8
Typo: s/caes/cases/ in SimplifyCFG

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183219 91177308-0d34-0410-b5e6-96231b3b80d8
Second part of pr16069

The problem this time seems to be a thinko. We were assuming that in the CFG

A
| \
|  B
| /
C

speculating the basic block B would cause only the phi value for the B->C edge
to be speculated. That is not true, the phi's are semantically in the edges, so
if the A->B->C path is taken, any code needed for A->C is not executed and we
have to consider it too when deciding to speculate B.

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R600: Add a test for r183108

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R600: Swizzle texture/export instructions

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Remove "-Wl,-seg1addr -Wl,0xE0000000" from link options.

Specifying the load address for Darwin i386 dylibs was a performance
optimization for dyld that is not relevant for x86_64 or arm. We can just
remove this now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183230 91177308-0d34-0410-b5e6-96231b3b80d8
ARM: Fix crash in ARM backend inside of ARMConstantIslandPass

The ARM backend did not expect LDRBi12 to hold a constant pool operand.
Allow for LLVM to deal with the instruction similar to how it deals with
LDRi12.

This fixes PR16215.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183238 91177308-0d34-0410-b5e6-96231b3b80d8
IndVarSimplify: check if loop invariant expansion can trap

IndVarSimplify is willing to move divide instructions outside of their
loop bodies if they are invariant of the loop.  However, it may not be
safe to expand them if we do not know if they can trap.

Instead, check to see if it is not safe to expand the instruction and
skip the expansion.

This fixes PR16041.

Testcase by Rafael Ávila de Espíndola.


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Sparc: No functionality change. Cleanup whitespaces, comment formatting etc.,


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Fix link.


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SubtargetEmitter fix

Don't output data if we are supposed to ignore the record.

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ARMInstrInfo: Improve isSwiftFastImmShift

An instruction with less than 3 inputs is trivially a fast immediate shift.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183256 91177308-0d34-0410-b5e6-96231b3b80d8
ARM sched model: Add divsion, loads, branches, vfp cvt

Add some generic SchedWrites and assign resources for Swift and Cortex A9.

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ARM sched model: Add more ALU and CMP instructions

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 ARM sched model: Add more ALU and CMP thumb2 instructions

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ARM sched model: Add more ALU and CMP thumb instructions

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ARM sched model: Add preload instructions

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