[mips][msa] Added most of the remaining builtins

Includes:
and.v, bmnz.v, bmz.v, bnz.[bhwdv], bz.[bhwdv], cfcmsa, ctcmsa, fcaf,
fcor, fcueq, fcul[et], fcun, fcune, fsaf, fsueq, fsul[et], fsun, fsune, ftrunc
hadd_[su].[hwd], hsub_[su].[hwd], insert.[bhw], insve.[bhw], ld.[bhwd],
move.v, nor.v, or.v, srar.[bhwd], srari.[bhwd], srlr.[bhwd], srlri.[bhwd],
st.[bhwd], subsus_u.[bhwd], subsuu_s.[bhwd], vshf.[bhwd], xor.v



git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@192896 91177308-0d34-0410-b5e6-96231b3b80d8
[mips][msa] Update -mmsa help text and removed the hidden flag to better match conventions used by other targets



git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@192898 91177308-0d34-0410-b5e6-96231b3b80d8
[mips] Added -mfp64 and -mfp32 options.

These options specify 64-bit FP registers and 32-bit FP registers respectively.

When using -mfp32, the FPU has 16x double-precision registers overlapping with
the 32x single-precision registers (each double-precision register overlaps
two single-precision registers).

When using -mfp64, the FPU has 32x double-precision registers overlapping with
the 32x single-precision registers (each double-precision register overlaps
with one single-precision register and has an additional 32-bits).

MSA requires -mfp64.



git-svn-id: https://llvm.org/svn/llvm-project/cfe/trunk@192899 91177308-0d34-0410-b5e6-96231b3b80d8