ARM: i.MX: Fix i.MX27 debug uart Kconfig entries

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
ARM: mxs: make ssp gates parents of ssp dividers

When changing the rates of the ssp clocks we have to poll the
busy bit, but only when they are enabled. The current code can
not check this properly since the gates are registered as children
of the dividers. This has the effect that when the gate is disabled
the busy bit will be set forever resulting in a freezed system.

Fix this by making the gates parents of the dividers which allows
clk_is_enabled to return the correct result.

The Kernel has the same problem, but here the busy polling is
limited to 10ms, so probably noone noticed this.

The datasheet mentions that the ssp dividers shall only be changed
when the clocks are enabled. The kernel and barebox currently ignore
this. I don't know what effect violating this rule has.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
commands: spi: Fix spi read procedure

Buffer for RX is set incorrectly.

barebox@Phytec phyCORE-i.MX27:/  spi -r 128 -v
device config
    bus_num       = 0
    max_speed_hz  = 1000000
    chip_select   = 0
    mode          = 0x0
    bits_per_word = 8

wrote 0 bytes
00000000:
read 128 bytes
00000000: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
00000010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
00000020: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
00000030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
00000040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
00000050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
00000060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
00000070: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00    ................
unable to handle paging request at address 0x4dffd3d0
pc : [<a7f05ec4>]    lr : [<a7f05ebc>]
sp : a7fff890  ip : a7fff860  fp : a7f68820
r10: a6ffe9bc  r9 : 00000000  r8 : 00000001
r7 : a6ffe9ec  r6 : a6f00000  r5 : a6ffe9ec  r4 : a6ffe9e4
r3 : a6ffe9e4  r2 : a6ffe9e5  r1 : a6ffe9e4  r0 : 4dffd3cc
Flags: nZCv  IRQs off  FIQs off  Mode SVC_32
...

Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>