target-arm: aarch64: add support for conditional branches

This patch adds emulation for the conditional branch (b.cond) instruction.

Signed-off-by: Alexander Graf <agraf@suse.de>

[claudio: adapted to new decoder structure,
          reused arm infrastructure for checking the flags]

Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>

From Alexander Graf <agraf@suse.de> aarch64 series 34/60
target-arm: aarch64: add support for conditional select

this patch adds support for "C3.5.6 Conditional select",
which means CSEL, CSINC, CSINV, CSNEG.

Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>

From Alexander Graf <agraf@suse.de> aarch64 series 43/60
default-configs: Add config for aarch64-linux-user

Add a config for aarch64-linux-user, thereby enabling it as
a valid target.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
translate-a64.c: add new-line to log message
translate-a64.c: dump subject pc on unalloc enc

This turns out to be fairly handy when you are trying to figure out how
far into the binary you have got.
.travis.yml: add aarch64-linux-user target
target-arm: aarch64: add support for add and addi

This patch combines two of the original series for generic add
implementation support.

from Alexander Graf <agraf@suse.de> aarch64 series 15/60 (- extended)
from Alexander Graf <agraf@suse.de> aarch64 series 27/60

---

v2 -> v3:

      - use extract32/sextract32 instead of get_bits and get_sbits
      - open code get_reg()

v3 -> v4 (ajb):
      - removed the flag handling helpers, stubbed out TCG equivalent
      - streamlined the generation to avoid duplication

v4 -> v5 (ajb):
      - used Claudio's common add_with_carry for flag ops
      - common as much as possible between addi/add
      - removed extraneous diagrams
      - documented the add (extended register) stub

v5 -> v6 (ajb):
      - drop add_with_carry for now
target-arm: aarch64: add support for stp (store pair)

This patch support basic GPR based store-pair instructions and includes
the generic do_gpr_st() function for store routines.

from Alexander Graf <agraf@suse.de> aarch64 series 11/60

---

v2 -> v3:

      - use extract32/sextract32 instead of get_bits and get_sbits
      - drop get_reg()
      - open code get_reg()

v3 -> v4
      - split from bigger patch (non vector)
      - better naming?
target-arm: aarch64: add support for movi

This patch adds emulation for the movi instruction. This includes the
various movn, movz and movk forms.

Signed-off-by: Alexander Graf <agraf@suse.de>

---

    v2 -> v3:

      - use extract32/sextract32 instead of get_bits and get_sbits
      - open code get_reg()

    v3 -> v4 (ajb):

       - applied RH's constant folding comment
       - move cpu_reg allocation to top
target-arm: aarch64: add support for ld/st unsigned imm

This adds support for the basic non-vector form of ld/st with and
unsigned immediate offset. This was split from the original patch from
Alexander due to re-factoring due to the changes in the decoder.

from Alexander Graf <agraf@suse.de> aarch64 series 41/60
target-arm: aarch64: add support for ld lit

Adds support for Load Register (literal).

from Alexander Graf <agraf@suse.de> aarch64 series 40/60