[LOCAL]: EDIT GCC/MAKEFILE.IN To avoid failures in parallel builds of core pass2

with errors relating to

optabs.h:25:25: error: insn-opinit.h: No such file or directory

BROKE in UPSTREAM, when fixed, can be removed

Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
[Patch, microblaze]: Enable DWARF exception handling support.

Changelog

2013-03-18  Edgar E. Iglesias <edgar.iglesias@xilinx.com>
            David Holsgrove <david.holsgrove@xilinx.com>

 * common/config/microblaze/microblaze-common.c: Remove
   TARGET_EXCEPT_UNWIND_INFO definition.
 * config/microblaze/microblaze-protos.h: Add
   microblaze_eh_return prototype.
 * gcc/config/microblaze/microblaze.c: (microblaze_must_save_register,
   microblaze_expand_epilogue, microblaze_return_addr): Handle
   calls_eh_return
   (microblaze_eh_return): New function.
 * gcc/config/microblaze/microblaze.h: Define RETURN_ADDR_OFFSET,
   EH_RETURN_DATA_REGNO, MB_EH_STACKADJ_REGNUM, EH_RETURN_STACKADJ_RTX,
   ASM_PREFERRED_EH_DATA_FORMAT
 * gcc/config/microblaze/microblaze.md: Define eh_return pattern.

Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
[Patch, microblaze]: Fix bswaphi2 implementation

MicroBlaze insn swaph swaps the contents of register rA
as two halfwords placing result in rD;

(rD)[0:15]  <- (rA)[16:31]
(rD)[16:31] <- (rA)[0:15]

gcc bswaphi2 is intended to reverse the order of the bytes
in the half integer in rA

(rD)[8:15]  <- (rA)[0:7]
(rD)[7:0]   <- (rA)[8:15]
(rD)[24:31] <- (rA)[16:23]
(rD)[16:23] <- (rA)[24:31]

Correct microblaze bswaphi2 insn pattern to be a
swapb followed by swaph

Reported-by: Nathan Rossi <nathan.rossi@xilinx.com>
Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
[Patch, microblaze]: Add 4 byte implementation for atomic builtin

By providing this initial atomic implementation, gcc is able to generate the other atomic
builtins by using a __sync_compare_and_swap loop

Add __sync_lock_test_and_set 4 byte atomic builtin

Changelog

2013-03-18  David Holsgrove <david.holsgrove@xilinx.com>

 * gcc/config/microblaze/sync.md: New file.
 * gcc/config/microblaze/microblaze.md: Add UNSPEC_SYNC_CAS,
   UNSPEC_SYNC_XCHG and include sync.md.
 * gcc/config/microblaze/microblaze.c: Add print_operand 'y'.
 * gcc/config/microblaze/constraints.md: Add memory_contraint
   'Q' which is a single register.

Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
[Patch, microblaze]: Rework sync builtins to atomic builtin

Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
[Patch, microblaze]: cstoresf4, add mode to insn pattern

Add SImode to comparison operator, prevents ICE during combine
rtl pass with error message;

internal compiler error: in simplify_subreg, at simplify-rtx.c:5725

Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
[Patch, microblaze]: Add TARGET_ASM_OUTPUT_MI_THUNK to support varargs thunk

Without this macro, generic gcc generates a less efficient thunk
that calls function instead of jumping to it. The generic code
does not support varargs and produces an error message on compilation;

 error: generic thunk code fails for method
 'virtual void C::f(const char*, ...)' which uses '...'

Also extend jump insn to accept bri to SYMBOL_REFS, as current insn
checks if operand is a REG - if so, uses br else it bri to %l0 - using a
label_ref print operand. Check if operand is a SYMBOL_REF, and if so,
use %0

Changelog

2013-03-18  David Holsgrove <david.holsgrove@xilinx.com>

 * gcc/config/microblaze/microblaze.c: Add microblaze_asm_output_mi_thunk
   and define TARGET_ASM_OUTPUT_MI_THUNK and TARGET_ASM_CAN_OUTPUT_MI_THUNK
 * gcc/config/microblaze/microblaze.md (jump):
   Account for jumps to SYMBOL_REFs.

Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
[Patch, microblaze]: Add -fstack-usage support

Changelog

2013-03-18  David Holsgrove <david.holsgrove@xilinx.com>

 * gcc/config/microblaze/microblaze.c (microblaze_expand_prologue):
   Add check for flag_stack_usage to enable -fstack-usage support

Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
[Patch, microblaze]: Remove SECONDARY_MEMORY_NEEDED

MicroBlaze doesn't have restrictions that would force us to
reload regs via memory. Don't define SECONDARY_MEMORY_NEEDED.
Fixes an ICE when compiling OpenSSL for linux.

Changelog

2013-03-18  Edgar E. Iglesias <edgar.iglesias@xilinx.com>

 * gcc/config/microblaze/microblaze.h: Remove SECONDARY_MEMORY_NEEDED
   definition.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Peter A. G. Crosthwaite <peter.crosthwaite@xilinx.com>
[Patch, microblaze]: Add SIZE_TYPE and PTRDIFF_TYPE to microblaze.h

Fixes warnings like;

warning: format '%zX' expects argument of type 'size_t',
but argument 3 has type 'unsigned int' [-Wformat]

Changelog

2013-03-18  David Holsgrove <david.holsgrove@xilinx.com>

 * gcc/config/microblaze/microblaze.h: Define SIZE_TYPE
   and PTRDIFF_TYPE.

Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
[Patch, microblaze]: Add branch_compare instruction

To facilitate optimization pass understanding of the conditional
branch for microblaze, remove the UNSPEC'd signed_compare /
unsigned_compare instructions, and replace with a complete
branch_compare which will output_asm_insn the correct cmp/cmpu
depending on comparison code and signed / unsigned.

We then return the correct branch instruction.

cbranchsi now calls an expanded microblaze_expand_conditional_branch
function which will carry out compare against zero, compare EQ/NE,
and all other compares appropriately.

-funroll-loops optimization pass can now proceed

Changelog

2013-03-19  David Holsgrove <david.holsgrove@xilinx.com>

 * gcc/config/microblaze/predicates.md: Add cmp_op predicate.
 * gcc/config/microblaze/microblaze.md: Add branch_compare
   instruction which uses cmp_op predicate and emits cmp insn
   before branch.
 * gcc/config/microblaze/microblaze.c
   (microblaze_emit_compare): Rename to
   microblaze_expand_conditional_branch and consolidate logic.
   (microblaze_expand_conditional_branch): emit branch_compare
   insn instead of handling cmp op separate from branch insn.

Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
[Patch, microblaze]: Disable fivopts by default

Turn off ivopts by default. Interferes with cse.

Changelog

2013-03-18  Edgar E. Iglesias <edgar.iglesias@xilinx.com>

 * gcc/common/config/microblaze/microblaze-common.c
   (microblaze_option_optimization_table): Disable fivopts by default.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
[Patch, microblaze]: Add INIT_PRIORITY support

Added TARGET_ASM_CONSTRUCTOR and TARGET_ASM_DESTRUCTOR macros.

These macros allows users to control the order of initialization
of objects defined at namespace scope with the init_priority
attribute by specifying a relative priority, a constant integral
expression currently bounded between 101 and 65535 inclusive.

Lower numbers indicate a higher priority.

Signed-off-by:nagaraju <nmekala@xilix.com>
Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
[Patch, microblaze]: Add optimized lshrsi3

When barrel shifter is not present, the immediate value
is greater than #5 and optimization is -OS, the
compiler will generate shift operation using loop.

Signed-off-by: [Nagaraju] [nmekala@xilinx.com>]
Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
[Patch, microblaze]: Add supervisory call support

A function can be executed in supervisory mode when a function
is declared with svc_handler attribute.

If a function with svc_handler is called, the processor switches
to supervisory mode and executes. After executing the function
it returns to normal mode.

Same feature can also be invoked with svc_table_handler attribute
but this attribute will accept a service ID, to be used for
calling the function.

Signed-off-by:nagaraju <nmekala@xilix.com>
Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
[Patch, microblaze]: Extended mcpu version format

Microblaze currently only supports mcpu version of
format vX.YY.Z

This patch extends the mcpu version format to include;

 vX.YY.Z
 vXX.YY.Z
 vXX.YY
 vX.YY.Z

Signed-off-by:nagaraju <nmekala@xilix.com>
Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
[Patch, microblaze]: Increase max ailgnment to please the testsuite

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
[Patch, microblaze]: Use bralid for profiler calls

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
[Patch, microblaze]: Add microblaze to check_profiling_available

Testsuite, add microblaze*-*-* target in check_profiling_available
inline with other archs setting profiling_available_saved to 0

Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
[LOCAL]: updated gcc.target/microblaze/others/strings1.c

for new scan-assembly output resulting in use of $LC label

Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>