[MIPS] Update fast TLB handler for new kernels

The Linux in memory PTE format changed for the 3.4 kernel.
This change handles both formats and should be more robust
against future changes.

(cherry picked from commit 6e22b2095d718a417cee9bb2d5b3a2cf4b3d9809)

Change-Id: I9bff0d96a999541b6c39df08a893905542a522f8
Prevent target code getting out of sync with Translation Blocks.

Fixes a problem where the target code gets out of sync
with the Translation Blocks (TB). LTP tests crash and QEMU
itself will crash eventually when generating new TB code
while searching for a PC in an existing TB. Debugging code
that checks that the target code and TB's are in sync confirm
that this change fixes the problem.

This is an import from git://git.qemu.org/qemu.git
    -----------------------------------------------------------------------
    commit 0b57e287138728f72d88b06e69b970c5d745c44a
    Author: David Gibson <david@gibson.dropbear.id.au>
    Date:   Mon Sep 10 12:30:57 2012 +1000

    cpu_physical_memory_write_rom() needs to do TB invalidates

    cpu_physical_memory_write_rom(), despite the name, can also be used to
    write images into RAM - and will often be used that way if the machine
    uses load_image_targphys() into RAM addresses.

    However, cpu_physical_memory_write_rom(), unlike cpu_physical_memory_rw()
    doesn't invalidate any cached TBs which might be affected by the region
    written.

    This was breaking reset (under full emu) on the pseries machine - we loaded
    our firmware image into RAM, and while executing it rewrite the code at
    the entry point (correctly causing a TB invalidate/refresh).  When we
    reset the firmware image was reloaded, but the TB from the rewrite was
    still active and caused us to get an illegal instruction trap.

    This patch fixes the bug by duplicating the tb invalidate code from
    cpu_physical_memory_rw() in cpu_physical_memory_write_rom().

    Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
    Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
    -----------------------------------------------------------------------

Signed-off-by: Chris Dearman <Chris.Dearman@imgtec.com>
Signed-off-by: Pete Delaney <piet.delaney@imgtec.com>
Signed-off-by: Duane Sand <Duane.Sand@imgtec.com>

(cherry picked from commit 82820720b5e36c9770227d12e688ea2d196ecfe4)

Change-Id: If01645191212e1be64ce63568755470034611a8f
exec: Introduce helper to set dirty flags.

NOTE: Cherry picked from git.qemu.org
      51d7a9eb2b64e787c90bea1027308087eac22065

This new helper/hook is used in the next patch to add
an extra call in a single place.

Signed-off-by: Anthony PERARD <anthony.perard@citrix.com>
Reviewed-by: Avi Kivity <avi@redhat.com>
Signed-off-by: Pete Delaney <piet.delaney@imgtec.com>
Signed-off-by: Chris Dearman <Chris.Dearman@imgtec.com>
Signed-off-by: Duane Sand <Duane.Sand@imgtec.com>

(cherry picked from commit d09d7665187911f9aedf0951818a45b7485acbb0)

Change-Id: I4b0fed81b21fa24b21e308aab21da4f81b470061
[MIPS] Support for DSP ASE in Android QEMU

This patch includes following changes from the main qemu trunk:

8b758d0 target-mips: fix rndrashift_short_acc and code for EXTR_ instructions
26135ea target-mips: Fix accumulator selection for MIPS16 and microMIPS
20c334a target-mips: fix DSP overflow macro and affected routines
a345481 target-mips: fix for sign-issue in MULQ_W helper
9c19eb1 target-mips: fix for incorrect multiplication with MULQ_S.PH
e62a214 target-mips: fix incorrect test for MTHLIP
6f0af30 target-mips: enable access to DSP ASE if implemented
df6126a target-mips: implement DSP (d)append sub-class with TCG
0a16c79 target-mips: use DSP unions for reduction add instructions
75d012a target-mips: use DSP unions for unary DSP operators
6de0e6c target-mips: use DSP unions for binary DSP operators
652613a target-mips: add unions to access DSP elements
ad153f1 target-mips: generate a reserved instruction exception on CPU without DSP
f7d2072 target-mips: fix DSP loads with rd = 0
da1a4ce target-mips: Fix helper and tests for dot/cross-dot product instructions
e1a4019 target-mips: Allow DSP access to be disabled once enabled.
c4aaba9 target-mips: Make repl_ph to sign extend to target-long
b8abbbe target-mips: Fix for helpers for EXTR_* instructions
eec8972 target-mips: Fix incorrect reads and writes to DSPControl register
19e6c50 target-mips: Fix incorrect shift for SHILO and SHILOV
34f5606 target-mips: Fix incorrect code and test for INSV
eec8972 target-mips: Fix incorrect reads and writes to DSPControl register
b30706d target-mips: Change TODO file
d70080c target-mips: Add ASE DSP testcases
af13ae0 target-mips: Add ASE DSP processors
b53371e target-mips: Add ASE DSP accumulator instructions
2669056 target-mips: Add ASE DSP compare-pick instructions
1cb6686 target-mips: Add ASE DSP bit/manipulation instructions
a22260a target-mips: Add ASE DSP multiply instructions
77c5fa8 target-mips: Add ASE DSP GPR-based shift instructions
461c08d target-mips: Add ASE DSP arithmetic instructions
9b1a1d6 target-mips: Add ASE DSP load instructions
e45a93e target-mips: Add ASE DSP branch instructions
853c324 target-mips: Add ASE DSP resources access check
235eb01 target-mips: Add ASE DSP internal functions

Also, it contains uncommited DSP fixes.

Change-Id: I6dd160d7a55de2bc896ff813b88f7729834d2517