FogBugz #112256: Adding block lock features for NAND

Adding NAND block lock and unlock features. This is only applicable
for Micron parts only. For those flash which locks all the blocks
upon power on, unlock commands are required prior erase and
write operations

Signed-off-by: Chin Liang See <clsee@altera.com>
---
Changes for v2
- Updated the commit message
FogBugz #163711: Enhancing Preloader semihosting function

Enhancing the semihosting function to ensure its working well
with various compilers. The enhancement will avoid incorrect
assumption being made between the call stack and function call.

Signed-off-by: Chin Liang See <clsee@altera.com>
FogBugz #112256: Reconfigure PLL for NAND and SDMMC controller

Reconfigure the PLL in order to supply 50MHz clock for NAND
which is the fastest clock. As that clock is shared with SDMMC,
SDMMC clock is speed up to 200MHz. Also fixed the invalid value
for SDRAM and EMAC clock info.

Signed-off-by: Chin Liang See <clsee@altera.com>
FogBugz #112256: Enable NAND ECC read within SPL framework

Enable the NAND ECC read within SPL. This is to take advantage
of HW ECC capabilities of some NAND controller such Denali. It
will avoid using software to manual calculating the ECC and
correct it. With this option, it will yield better performance
for NAND access within SPL framework.

Signed-off-by: Chin Liang See <clsee@altera.com>
FogBugz #112256: Adding Denali NAND configuration

Adding the Denali NAND controller configuration. But it will
not enabled by default as NAND is not available within Altera
Dev Kit. Please refer to doc/README.SOCFPGA for more details.

Signed-off-by: Chin Liang See <clsee@altera.com>
FogBugz #159335: Enhance Arria V SDRAM to 533MHz

Enhancing the Arria V SDRAM from 400MHz to 533MHz.

Signed-off-by: Chin Liang See <clsee@altera.com>
FogBugz #158537: Updating U-Boot FPGA2SDRAM driver

To update the U-Boot FPGA2SDRAM enablement driver where applycfg
bit need to be set after write to fpgaportrst. At same time, the
applycfg bit can be set only the SDRAM is in idle mode. With
that, the code to set the applycfg will be execute in OCRAM

Signed-off-by: Chin Liang See <clsee@altera.com>
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Changes for v2
- used macro for mask
- updated commit message
FogBugz #163055: Fixing Preloader FPGA programming

To fix the Preloader FPGA programming issue due to recent
enhancement. This is to avoid programming additional words
into FPGA. At same time, update the FPGA2SDRAM port release
code after the FPGA programming.

Signed-off-by: Chin Liang See <clsee@altera.com>
FogBugz #136143: Enhancing Preloader SDRAM memory test

To enhance the existing SDRAM memory test. Added a memory
test which is utilizing the PRBS (pseudo-random binary sequence)
algorithm. At same time, ensure lowest memory map is mapped to
SDRAM so it can be tested too.

Signed-off-by: Chin Liang See <clsee@altera.com>
---
Changes for v4
- Removed redundant code
Changes for v3
- reshuffled the condition check for coverage within SDRAM test
Changes for v2
- used macro to determine the SDRAM test coverage
- updated comments
FogBugz #163509: Enhancing QSPI access performance

To enhance QSPI driver function which check for controller status.
Using the timeout method instead of fixed delay when polling
the controller status to reach idle state.

Signed-off-by: Chin Liang See <clsee@altera.com>
---
Changes for v3
- updated the commit message
Changes for v2
- updated the commit message