ARM: 7668/1: fix memset-related crashes caused by recent GCC (4.7.2) optimizations

Recent GCC versions (e.g. GCC-4.7.2) perform optimizations based on
assumptions about the implementation of memset and similar functions.
The current ARM optimized memset code does not return the value of
its first argument, as is usually expected from standard implementations.

For instance in the following function:

void debug_mutex_lock_common(struct mutex *lock, struct mutex_waiter *waiter)
{
	memset(waiter, MUTEX_DEBUG_INIT, sizeof(*waiter));
	waiter->magic = waiter;
	INIT_LIST_HEAD(&waiter->list);
}

compiled as:

800554d0 <debug_mutex_lock_common>:
800554d0:       e92d4008        push    {r3, lr}
800554d4:       e1a00001        mov     r0, r1
800554d8:       e3a02010        mov     r2, #16 ; 0x10
800554dc:       e3a01011        mov     r1, #17 ; 0x11
800554e0:       eb04426e        bl      80165ea0 <memset>
800554e4:       e1a03000        mov     r3, r0
800554e8:       e583000c        str     r0, [r3, #12]
800554ec:       e5830000        str     r0, [r3]
800554f0:       e5830004        str     r0, [r3, #4]
800554f4:       e8bd8008        pop     {r3, pc}

GCC assumes memset returns the value of pointer 'waiter' in register r0; causing
register/memory corruptions.

This patch fixes the return value of the assembly version of memset.
It adds a 'mov' instruction and merges an additional load+store into
existing load/store instructions.
For ease of review, here is a breakdown of the patch into 4 simple steps:

Step 1
======
Perform the following substitutions:
ip -> r8, then
r0 -> ip,
and insert 'mov ip, r0' as the first statement of the function.
At this point, we have a memset() implementation returning the proper result,
but corrupting r8 on some paths (the ones that were using ip).

Step 2
======
Make sure r8 is saved and restored when (! CALGN(1)+0) == 1:

save r8:
-       str     lr, [sp, #-4]!
+       stmfd   sp!, {r8, lr}

and restore r8 on both exit paths:
-       ldmeqfd sp!, {pc}               @ Now <64 bytes to go.
+       ldmeqfd sp!, {r8, pc}           @ Now <64 bytes to go.
(...)
        tst     r2, #16
        stmneia ip!, {r1, r3, r8, lr}
-       ldr     lr, [sp], #4
+       ldmfd   sp!, {r8, lr}

Step 3
======
Make sure r8 is saved and restored when (! CALGN(1)+0) == 0:

save r8:
-       stmfd   sp!, {r4-r7, lr}
+       stmfd   sp!, {r4-r8, lr}

and restore r8 on both exit paths:
        bgt     3b
-       ldmeqfd sp!, {r4-r7, pc}
+       ldmeqfd sp!, {r4-r8, pc}
(...)
        tst     r2, #16
        stmneia ip!, {r4-r7}
-       ldmfd   sp!, {r4-r7, lr}
+       ldmfd   sp!, {r4-r8, lr}

Step 4
======
Rewrite register list "r4-r7, r8" as "r4-r8".

Change-Id: I79a0d6897572b693d50f8ea8a94aa331bfcc59f8
Git-Commit: 455bd4c430b0c0a361f38e8658a0d6cb469942b5
Git-Repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
Signed-off-by: Ivan Djelic <ivan.djelic@parrot.com>
Reviewed-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Dirk Behme <dirk.behme@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
Signed-off-by: franciscofranco <franciscofranco.1990@gmail.com>
ARM: 7670/1: fix the memset fix

Commit 455bd4c430b0 ("ARM: 7668/1: fix memset-related crashes caused by
recent GCC (4.7.2) optimizations") attempted to fix a compliance issue
with the memset return value.  However the memset itself became broken
by that patch for misaligned pointers.

This fixes the above by branching over the entry code from the
misaligned fixup code to avoid reloading the original pointer.

Also, because the function entry alignment is wrong in the Thumb mode
compilation, that fixup code is moved to the end.

While at it, the entry instructions are slightly reworked to help dual
issue pipelines.

Change-Id: I5db45a7de1e389bacb5d6e4513c0d446ae2c9440
Git-Commit: 418df63adac56841ef6b0f1fcf435bc64d4ed177
Git-Repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
Signed-off-by: Nicolas Pitre <nico@linaro.org>
Tested-by: Alexander Holler <holler@ahsoftware.de>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Stepan Moskovchenko <stepanm@codeaurora.org>
Signed-off-by: franciscofranco <franciscofranco.1990@gmail.com>
msm: idle-v7: flush non secure L1 cache lines for l2 GDHS LPM mode

It is LPM driver(HLOS) responsiblity to flush non secure lines of
L1 cache when the core decide to enter a LPM mode where core get
powered off. But current code is not flushing the non secure lines
of L1 cache when the core decide to enter into L2 GDHS LPM mode.
This change addresses the flushing of non secure lines of L1 cache.

CRs-fixed: 555905
Change-Id: I721947386091875994bcb71bd8b9b9b793a72349
Signed-off-by: Murali Nalajala <mnalajal@codeaurora.org>
Signed-off-by: franciscofranco <franciscofranco.1990@gmail.com>
sched: Fix clear NOHZ_BALANCE_KICK

I have faced a sequence where the Idle Load Balance was sometime not
triggered for a while on my platform, in the following scenario:

 CPU 0 and CPU 1 are running tasks and CPU 2 is idle

 CPU 1 kicks the Idle Load Balance
 CPU 1 selects CPU 2 as the new Idle Load Balancer
 CPU 2 sets NOHZ_BALANCE_KICK for CPU 2
 CPU 2 sends a reschedule IPI to CPU 2

 While CPU 3 wakes up, CPU 0 or CPU 1 migrates a waking up task A on CPU 2

 CPU 2 finally wakes up, runs task A and discards the Idle Load Balance
       task A quickly goes back to sleep (before a tick occurs on CPU 2)
 CPU 2 goes back to idle with NOHZ_BALANCE_KICK set

Whenever CPU 2 will be selected as the ILB, no reschedule IPI will be sent
because NOHZ_BALANCE_KICK is already set and no Idle Load Balance will be
performed.

We must wait for the sched softirq to be raised on CPU 2 thanks to another
part the kernel to come back to clear NOHZ_BALANCE_KICK.

The proposed solution clears NOHZ_BALANCE_KICK in schedule_ipi if
we can't raise the sched_softirq for the Idle Load Balance.

Change since V1:

- move the clear of NOHZ_BALANCE_KICK in got_nohz_idle_kick if the ILB
  can't run on this CPU (as suggested by Peter)

Signed-off-by: Vincent Guittot <vincent.guittot@linaro.org>
Signed-off-by: Peter Zijlstra <peterz@infradead.org>
Link: http://lkml.kernel.org/r/1370419991-13870-1-git-send-email-vincent.guittot@linaro.org
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Git-commit: 873b4c65b519fd769940eb281f77848227d4e5c1
Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
[smuckle@codeaurora.org: minor merge resolution for 3.4 in scheduler_ipi()]
Signed-off-by: Steve Muckle <smuckle@codeaurora.org>
Change-Id: I3548612057cccc2ecc29429c129c44183083831f

Signed-off-by: Francisco Franco <franciscofranco.1990@gmail.com>
cpufreq: interactive: fallback to previous new_freq calculation as it is much more conservative. Also fix the new_freq logic, specially if boosted is true.

Signed-off-by: Francisco Franco <franciscofranco.1990@gmail.com>
cfg80211: Fix memory leak

When a driver requests a specific regulatory domain after cfg80211 already
has one, a struct ieee80211_regdomain is leaked.

Change-Id: Id28fc9861b9c911a97bd242439eabca097d76258
Reported-by: Larry Finger <Larry.Finger@lwfinger.net>
Tested-by: Larry Finger <Larry.Finger@lwfinger.net>
Signed-off-by: Larry Finger <Larry.Finger@lwfinger.net>
Signed-off-by: Johannes Berg <johannes.berg@intel.com>
Git-commit: b7566fc363e23f0efd3fa1e1460f9421cdc0d77e
Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
[mattw@codeaurora.org: trivially backport to the msm-3.4 kernel]
Signed-off-by: Matt Wagantall <mattw@codeaurora.org>

Signed-off-by: franciscofranco <franciscofranco.1990@gmail.com>
cpufreq: interactive: Add a sampling_down_factor for max frequencies

Change min_sample_time to 100ms when running at max

Change-Id: Ia7e35b0625bedf20e7ef3a1f52e5828ffbfed93e
Signed-off-by: Rohit Gupta <rohgup@codeaurora.org>
Signed-off-by: franciscofranco <franciscofranco.1990@gmail.com>
cpufreq: interactive: qqueue input boost to a high priority workqueue instead of having it go through the kthread speedchange path. This saves us spinlocks/unlocks everytime there's a touch and it saves us a couple ms to wait until the kthread is woken, then going through its code path, then the calculations, then finally calling the cpufreq target function. I measured a couple ms improvements in terms of responsiveness after touching the display and having cpufreq boosting the online cpus.

Signed-off-by: franciscofranco <franciscofranco.1990@gmail.com>
mdp: flo: Set minimum IB value for 4 layers

For 4 layer MDP composition, if the total composed area
doesn't cover the whole screen, there is a potential hole
in our calculation where we don't request enough bandwidth
especially for larger displays such as flo.
Pin the minimum bandwidth to ~1.6G (empirical) to fix this.

Bug: 10954796
Signed-off-by: Naseer Ahmed <naseer@codeaurora.org>
Signed-off-by: franciscofranco <franciscofranco.1990@gmail.com>
msm: kgsl: Update dispatcher/server-side sync

Refresh the dispatcher/server-side sync code with some general
fixes to functionality, stability and fault tolerance.

Change-Id: Ic0dedbad48161513a2670d3949fccbdbf14b8dff
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Carter Cooper <ccooper@codeaurora.org>
Signed-off-by: franciscofranco <franciscofranco.1990@gmail.com>
msm: kgsl: Allow sync points to be created on the submitter's context

There are situations where a submitting thread may wish to create a
syncpoint on an already issued timestamp to pause a context until a
previous command has been retired.  Relax the restriction against
submitting a sync point against one's own context and only check to
make sure the user isn't submitting a syncpoint against a future
timestamp (which would be an certain deadlock).

Change-Id: Ic0dedbad883fc228da0d94c8416a88504f5d1377
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: franciscofranco <franciscofranco.1990@gmail.com>
msm: kgsl: consolidate preamble based context switch code

Move logic for handling preamble based context switch
to the core adreno code. This makes it less burdensome
to implement support for newer GPU families that won't
ever support legacy context switching.

Change-Id: Id9ad5936ff91dcdbc9de869baf0d0b9fcf1b5170
Signed-off-by: Jeremy Gebben <jgebben@codeaurora.org>
Signed-off-by: franciscofranco <franciscofranco.1990@gmail.com>
msm: kgsl: Add IB submission gate for device suspend

Add IB submission gate to stop the system from making requests
while suspend is requested.  This will force users to wait for
the system to resume before making more requests.

Change-Id: I2460ef9b4237b586a31d4cea64b6dd74d30b08d9
Signed-off-by: Carter Cooper <ccooper@codeaurora.org>
Signed-off-by: franciscofranco <franciscofranco.1990@gmail.com>
msm: kgsl: Do not take active_cnt for events and waittimestamp

In the mists of time it was nessesary to take an active count
for waittimestamp and events because we did not want to run
the risk of suspending while the GPU was active.  Now that we
have the dispatcher we have much better control over the GPU
so the original risk is diminished.

The problem is that holding active_cnt prevents us from going
into nap and suspend and with server-side-sync a lot of the
events we are waiting for might take a very long time before
they even get dispatched on the GPU so we are essentially
keeping the clocks on waiting for other people.

z180 must take active count on its own.

Change-Id: Ic0dedbadcb608115938b198faebe333d19c6a8f6
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: franciscofranco <franciscofranco.1990@gmail.com>
msm: kgsl: always check kgsl_active_count_get() result

Getting an active count can fail if the hardware doesn't
actually wake up. Make active count get functions __mustcheck
to remind people of this and fix existing calls to
handle the error.

Change-Id: I5a0202c824ac7e436b9061da6d8f638e44e8b7f6
Signed-off-by: Jeremy Gebben <jgebben@codeaurora.org>
Signed-off-by: franciscofranco <franciscofranco.1990@gmail.com>
msm: kgsl: manage active count in adreno_ioctl()

Most of the adreno specific ioctls do not need the hardware
on. The few that do are perfcounter related, it may be
better at some point to optimize them further to shadow
the counters when the hardware is not on rather than
forcing the power on.

Change-Id: I9ea83106e0aaf3d3ac8d261bdec4e4c2e21c4659
Signed-off-by: Jeremy Gebben <jgebben@codeaurora.org>
Signed-off-by: franciscofranco <franciscofranco.1990@gmail.com>
msm: kgsl: remove KGSL_IOCTL_WAKE from context destruction

Adreno context destruction never needs the hardware on
to destroy the current context.

For z180, always take an active count while destroying.

Since this is the last ioctl to use KGSL_IOCTL_WAKE, remove
it entirely.

Change-Id: I97368c7f3c28f16538cc5f48b802b681d7af96ef
Signed-off-by: Jeremy Gebben <jgebben@codeaurora.org>
Signed-off-by: franciscofranco <franciscofranco.1990@gmail.com>
msm: kgsl: Run the idle timer while the GPU is not power collapsed

If the GPU is not in its lowest permitted power collapse state,
make sure there is a timer running to get the GPU to that state.

Change-Id: If57aaaf02087036bc4e24725c0cd3de5bc1f1034
Signed-off-by: Lucille Sylvester <lsylvest@codeaurora.org>
Signed-off-by: franciscofranco <franciscofranco.1990@gmail.com>
audio: asoc: headset: fix build-in mic recording fail.

During build-in mic recording, insert or remove headphone would
cause LDO_H power down which leads to recording fail.

Power on or down LDO_H by checking dapm widget LDO_H status.

Bug: 11523570

Change-Id: Ib7558748c093b60830eb41b2171c2eae95e4ed0a
Signed-off-by: sam_chen <sam_chen@asus.com>
Signed-off-by: franciscofranco <franciscofranco.1990@gmail.com>
msm: kgsl: update kgsl_cmdbatch_destroy with the tip

The kgsl_cmdbatch_destroy function is outdated with the tip and
the difference patch cannot be cherry-picked easily.

Signed-off-by: Jeff Boody <jboody@codeaurora.org>
Signed-off-by: franciscofranco <franciscofranco.1990@gmail.com>