Add SchedRW as an Instruction field.

Don't require instructions to inherit Sched<...>. Sometimes it is more
convenient to say:

  let SchedRW = ... in {
    ...
  }

Which is now possible.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177199 91177308-0d34-0410-b5e6-96231b3b80d8
Define more SchedWrites for annotating X86 instructions.

Since almost all X86 instructions can fold loads, use a multiclass to
define register/memory pairs of SchedWrites.

An X86FoldableSchedWrite represents the register version of an
instruction. It holds a reference to the SchedWrite to use when the
instruction folds a load.

This will be used inside multiclasses that define rr and rm instruction
versions together.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177210 91177308-0d34-0410-b5e6-96231b3b80d8
Add X86 code emitter support AVX encoded MRMDestReg instructions.

Previously we weren't skipping the VVVV encoded register. Based on patch by Michael Liao.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177221 91177308-0d34-0410-b5e6-96231b3b80d8
Test case for graceful handling of long file names on Windows.  Patch thanks to Paul Robinson!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177223 91177308-0d34-0410-b5e6-96231b3b80d8
[docs] Discuss a potential bug to be aware of.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177224 91177308-0d34-0410-b5e6-96231b3b80d8
Machine model. Allow mixed itinerary classes and SchedRW lists.

We always supported a mixture of the old itinerary model and new
per-operand model, but it required a level of indirection to map
itinerary classes to SchedRW lists. This was done for ARM A9.

Now we want to define x86 SchedRW lists, with the goal of removing its
itinerary classes, but still support the itineraries in the mean
time. When I original developed the model, Atom did not have
itineraries, so there was no reason to expect this requirement.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177226 91177308-0d34-0410-b5e6-96231b3b80d8
Change the default latency for implicit defs.

Implicit defs are not currently positional and not modeled by the
per-operand machine model. Unfortunately, we treat defs that are part
of the architectural instruction description, like flags, the same as
other implicit defs. Really, they should have a fixed MachineInstr
layout and probably shouldn't be "implicit" at all.

For now, we'll change the default latency to be the max operand
latency. That will give flag setting operands full latency for x86
folded loads. Other kinds of "fake" implicit defs don't occur prior to
regalloc anyway, and we would like them to go away postRegAlloc as
well.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177227 91177308-0d34-0410-b5e6-96231b3b80d8
Remove PPC avoidWriteAfterWrite callback

As a follow-up to r158719, remove PPCRegisterInfo::avoidWriteAfterWrite.
Jakob pointed out in response to r158719 that this callback is currently unused
and so this has no effect (and the speedups that I thought that I had observed
as a result of implementing this function must have been noise).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177228 91177308-0d34-0410-b5e6-96231b3b80d8
Remove FIXMEs in PPC test cases related to unaligned loads/stores

As pointed out by Bill in response to r177160, these two FIXMEs
can also be removed.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177229 91177308-0d34-0410-b5e6-96231b3b80d8
Improve PPC VR (Altivec) register spilling

This change cleans up two issues with Altivec register spilling:

  1. The spilling code was inefficient (using two instructions, and add and a
     load, when just one would do)

  2. The code assumed that r0 would always be available (true for now, but this
     will change)

The new code handles VR spilling just like GPR spills but forced into r+r mode.
As a result, when any VR spills are present, we must now always allocate the
register-scavenger spill slot.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177231 91177308-0d34-0410-b5e6-96231b3b80d8
The promised test case for r175939.

This test makes sure that the ObjCARC escape analysis looks at the uses of
instructions which copy the block pointer value by checking all four cases where
that can occur.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177232 91177308-0d34-0410-b5e6-96231b3b80d8
Build LLVMgold.so on FreeBSD using cmake.
Patch by Stephen Checkoway.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177233 91177308-0d34-0410-b5e6-96231b3b80d8
To avoid symbol clash, undefine PPC here. PPC may be predefined on some hosts.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177234 91177308-0d34-0410-b5e6-96231b3b80d8
Use ArrayRef<MVT::SimpleValueType> when possible.

Not passing vector references around makes it possible to use
SmallVector in most places.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177235 91177308-0d34-0410-b5e6-96231b3b80d8
Improve DIFile debug info annotation by letting it fallback to DIScope

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177236 91177308-0d34-0410-b5e6-96231b3b80d8
Generalize debug info test to be resilient to changes in metadata node numbering

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177238 91177308-0d34-0410-b5e6-96231b3b80d8
Split out filename & directory from DIFile to start generalizing over DIScopes

This is the first step to making all DIScopes have a common metadata prefix (so
that things (using directives, for example) that can appear in any scope can be
added to that common prefix). DIFile is itself a DIScope so the common prefix
of all DIScopes cannot be a DIFile - instead it's the raw filename/directory
name pair.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177239 91177308-0d34-0410-b5e6-96231b3b80d8
Reduced dont-infinite-loop-during-block-escape-analysis.ll with bugpoint and moved it to retain-block-escape-analysis.ll.

*NOTE* I verified that the original bug behind
dont-infinite-loop-during-block-escape-analysis.ll occurs when using opt on
retain-block-escape-analysis.ll.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177240 91177308-0d34-0410-b5e6-96231b3b80d8
Fix the build broken in r177239

Seems some accidental C++11 crept in there. Reported by the C++98 buildbots.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177241 91177308-0d34-0410-b5e6-96231b3b80d8
Refactor some duplicated code into helper functions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177242 91177308-0d34-0410-b5e6-96231b3b80d8