debugger: add the basics of a debugger.

Currently this just single-steps the simulation over a TCP socket though
the hooks are there for register accesses + running and stopping.  We'll
build it out with a Lua interface for scripting.
verif/debug: add socket connection to VPI model.

This allows a debugger to perform write accesses to the debug control
unit.  No readback support yet.
rtl/cpu: cleanup forwarding logic.

No functional changes, just source tidying.