x86: AVX2 deblock strength

30->18 cycles
x86: AVX2 high bit-depth intra_sad_x3_8x8

43->24 cycles
x86: AVX2 intra_sad_x3_8x8c

30->22 cycles
x86-64: faster SSSE3 trellis

~2% faster trellis.
x86: faster AVX2 quant_4x4x4

10->9 cycles
x86: faster SSSE3 hpel

~7% faster using the pmulhrsw trick from mc_chroma.
x86: Faster high bit-depth intra_sad_x3_4x4

20->16 cycles on Ivy Bridge
x86: AVX2 add16x16_idct_dc

27 -> 19 cycles
x86: 32-byte align the stack if possible

Avoids the need for manual 32 byte array alignment on compilers that support
-mpreferred-stack-boundary.
x86: Add missing initializations for high bit-depth sad_aligned
x86: Don't use explicitly aligned versions of SAD on AVX CPUs

On modern CPUs movdqu isn't slower than movdqa when used on aligned data and using the same code in both cases saves cache.

This was already done for the high bit-depth AVX2 implementation but the aligned version still exists as dead code so remove that.
checkasm: Use 64-bit cycle counters

Prevents overflows that can occur in some cases.
x86: AVX2 high bit-depth quant

quant_4x4: 13->6 cycles
quant_4x4_dc: 14->8 cycles
quant_8x8: 47->24 cycles
quant_4x4x4: 48->25 cycles