A more complicated method of dealing with D-type indeterminacy and device declaration order. Needs plenty of testing.

All output signals are now double-buffered - changes to output->sig are now visible to other devices only during the next machine cycle, and never during the same machine cycle that the changes were made in. This completely removes all effects of the order of devices.

Clocks modified slightly so that they follow the same low->rising->high pattern as other devices in the machinecycles trace output (also, they probably no longer need to go at the end of the list, but I'll leave that unchanged for now).

D-types now check specifically for changes in the input immediately before, during, and immediately after the rising clock edge, and should be indeterminate in all cases. Option added to print warnings when D-type output is indeterminate.