Added a comma in the ports list
fixed wishbone_mem_interconnect.v and script errors
Fixed some typos in logic analyzer core
Fixed some errors in the wb_sdram module
imported changed from xilinx_builder
Fixed names being messed up due to change of naming convention
Fixed some names messed up in the gen_top.py script
Fixed some verilog generation bugs
Added a generic cross clock enable core
Changed the name of the debug port to o_ftdi_debug
adjusted the sdram core to use cross_clock_enable

Originally I used a signal eminating from the ppfifo to indicate that it
was completely empty and thus a write was finished but, I can't remember
when, but I changed the behaviour of the ppfifo and removed the internal
signal. The SDRAM used this signal so in order to make up for that I had
to introduce a cross clock enable
Fixed a possible problem with the inactie signal

It was possible that the inactive signal would go high when the PPFIFO
wasn't truely inactive so I added another condition which will only
assert the inactive when both the read and write side are completely
empty
Fixed an oddity with the UCF file
Fixed a mistake on the names of the ftdi_suspend
Added support for reading periods
A lot of reworking this file

This file is way too big, it needs to be split up. since the new naming
convention where the port direction prepends port names, wires start
with w_'s and registers start with r_'s I've had a hard time finding all
the small bugs with the design, and this one was very hard. I added a
new fuction that will generate the io buffer

I changed the spacing to 4 instead of 2 for indents to align with PEP8