cli: Adding extra functionality.

lib: Added device path to bladerf structure to know where fd is pointing.
cli: peek/poke an print/set combined into single files.

Also added top level .gitignore file.
kernel: Changing USB VID/PID to OpenMoko instead of Cypress.
cli: Implemented bandwidth set/print
cli: Implemented txvga1 print/set and fixed library calls for txvga1.
cli: More print/set updated.
lib: Moved all implementation code to bladerf.c
hdl: Changed LED's to have different clocks.

LED 1 = pclk
LED 2 = lms_rx_clock_out
LED 3 = lms_rx_iq_select
lib: Allow reloading of FPGA
cli: Adding aliases to the commandline
cli: Added lnagain.
cli: Added rxvga1 and rxvga2.
lib: Modified calls to rxvga2 since units are in 3dB increments.
cli: Exit cleanly on SIGTERM, SIGINT, and SIGQUIT
cli: Formatting of poke changed to match peek.
cli: Added gpio printing.
fx3_firmware: disable multi DMA channel utilization for TX

Currently the FPGA tells the FX3 which of 4 (2 for RX and 2 for TX) "threads" to
use. These threads are actually hardware DMA engines. When multi DMAing occurs
for TX, 0-indexed DMA threads 2 and 3 are interleaved to copy data from the USB
to the FX3 GPIF port. However, there appears to be a bug in this interface
because as thread 2 is running, it will display the first word of thread 3
momentarily. The current solution is to downgrade to using a singel DMA channel,
which can easily handle upwards of 200MB/s of data per second; hence there
should be no performance hit.
hdl: fix TX path so that it only uses DMA thread 3

This commit contains the HDL fixes neccessary to make the FPGA only use DMA
thread 3.
fx3_firmware: disable multi DMA channel utilization for RX

This commit makes the FX3 default to using DMA thread 0 as the single DMA engine
for transferring RX samples. The reason is the same as for the TX thread change
2 commits ago.
hdl: fix RX path so that it only uses DMA thread 0

This commit contains the HDL fixes neccessary to make the FPGA only use DMA
thread 0 for RX.
hdl: change TX and RX clock sources

Production bladeRFs board use different clock sources for RX and TX, this
commits reflects these changes.
fpga: Adding rx signals signaltap file.