X86 fast-isel: Avoid explicit AH subreg reference for [SU]Rem.

Explicit references to %AH for an i8 remainder instruction can lead to
references to %AH in a REX prefixed instruction, which causes things to
blow up. Do the same thing in FastISel as we do for DAG isel and instead
shift %AX right by 8 bits and then extract the 8-bit subreg from that
result.

rdar://14203849
http://llvm.org/bugs/show_bug.cgi?id=16105

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185899 91177308-0d34-0410-b5e6-96231b3b80d8
X86: Add comment.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185900 91177308-0d34-0410-b5e6-96231b3b80d8
Move some code out of line. No functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185901 91177308-0d34-0410-b5e6-96231b3b80d8
Remove declare but not implemented methods.

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Compute the size of an archive member in the constructor.

It is always computed the same way (by parsing the header). Doing it in the
constructor simplifies the callers a bit.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185905 91177308-0d34-0410-b5e6-96231b3b80d8
PPC: Allocate RS spill slot for unaligned i64 load/store

This fixes another bug found by llvm-stress!

If we happen to be doing an i64 load or store into a stack slot that has less
than a 4-byte alignment, then the frame-index elimination may need to use an
indexed load or store instruction (because the offset may not be a multiple of
4, a requirement of the STD/LD instructions). The extra register needed to hold
the offset comes from the register scavenger, and it is possible that the
scavenger will need to use an emergency spill slot. As a result, we need to
make sure that a spill slot is allocated when doing an i64 load/store into a
less-than-4-byte-aligned stack slot.

Because test cases for things like this tend to be fairly fragile, I've
concatenated a few small bugpoint-reduced test cases together to form the
regression test.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185907 91177308-0d34-0410-b5e6-96231b3b80d8
InstCombine: add more transforms

C1-X <u C2 -> (X|(C2-1)) == C1
C1-X >u C2 -> (X|C2) == C1
X-C1 <u C2 -> (X & -C2) == C1
X-C1 >u C2 -> (X & ~C2) == C1


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185909 91177308-0d34-0410-b5e6-96231b3b80d8
Commit r185909 was a misapplied patch, fix it


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[PowerPC] Support .llong and fix .word

This adds support for the .llong PowerPC-specifc assembler directive.
In doing so, I notices that .word is currently incorrect: it is
supposed to define a 2-byte data element, not a 4-byte one.



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InstCombine: X & -C != -C -> X <= u ~C

Tests were added in r185910 somehow.


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InstCombine: variations on 0xffffffff - x >= 4

The following transforms are valid if -C is a power of 2:
(icmp ugt (xor X, C), ~C) -> (icmp ult X, C)
(icmp ult (xor X, C), -C) -> (icmp uge X, C)

These are nice, they get rid of the xor.


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InstCombine: Fix typo in comment for visitICmpInstWithInstAndIntCst


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[SystemZ] Use "STC;MVC" for memset

Use "STC;MVC" for memsets that are too big for two STCs or MV...Is yet
small enough for a single MVC.  As with memcpy, I'm leaving longer cases
till later.

The number of tests might seem excessive, but f33 & f34 from memset-04.ll
failed the first cut because I'd not added the "?:" on the calculation
of Size1.


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[SystemZ] Use MVC for simple load/store pairs

Look for patterns of the form (store (load ...), ...) in which the two
locations are known not to partially overlap.  (Identical locations are OK.)
These sequences are better implemented by MVC unless either the load or
the store could use RELATIVE LONG instructions.

The testcase showed that we weren't using LHRL and LGHRL for extload16,
only sextloadi16.  The patch fixes that too.


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Add MC assembly/disassembly support for VCVT{A, N, P, M} to V8FP.


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Revert r185872 - "Stop emitting weak symbols into the "coal" sections"

This patch broke `make check-asan` on Mac, causing ld warnings like the following one:

ld: warning: direct access in __GLOBAL__I_a to global weak symbol
___asan_mapping_scale means the weak symbol cannot be overridden at
runtime. This was likely caused by different translation units being
compiled with different visibility settings.

The resulting test binaries crashed with incorrect ASan warnings.


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[PowerPC] Support ".machine any"

The PowerPC assembler is supposed to provide a directive .machine
that allows switching the supported CPU instruction set on the fly.
Since we do not yet check CPU feature sets at all and always accept
any available instruction, this is not really useful at this point.

However, it makes sense to accept (and ignore) ".machine any" to
avoid spuriously rejecting existing assembler files that use this.



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Document LLVM_USE_SANITIZER CMake option

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Add MC assembly/disassembly support for VRINT{Z, X, R} to V8FP.


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Add MC assembly/disassembly support for VRINT{A, N, P, M} to V8FP.


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