Beta with some instructions that might work.
Some testing stuff. Runs an infinite loop!
Second half of prior commit.
Some cleanup.
Runs the final project checkoff.
Kludge it enough to run lab 5.
Shifted disassembly logic.
Built up some more convincing UI.
Run lab 8 properly

- Implemented interrupts
- Implemented keyboard input
- Implemented mouse input
- Throttle tty updates (less stuttering)
- Make it clear when in supervisor/user mode
- Stuff
Fix lab 7

- Removed complaint about illegal instructions in supervisor mode
- Forcibly align memory accesses to word boundaries.
- Implement TIME().
Convenient drag/drop file loading.
Merge branch 'master' of https://github.com/terman/6.004x into server_and_bootstrap
Moved into subdirectory.
Start working on actual bsim UI.
Merge old bsim simulation repo into this repo.
parse subcircuit hopefully implemented nicely
bsim: fix an issue with contentless-but-not-empty lines in the assembler.
Merged simulator and assembler into split-pane interface.
better error checking
wednesday morning commit