Fixed a test failure that occurs when the specified font is not installed.

On systems where 'Liberation Sans' is not installed out-of-the-box
(e.g. Ubuntu Server, OpenSuse Server) it falls back to 'DejaVu Sans',
which makes the GetHashCode_NameDiffers_HashesNotEqual() test fail as
the two font names are now equal. Instead we use 'Arial' and 'Courier New'
which resolve to different fonts on most systems.

Changes licensed under MIT/X11.
[Bug 16267] SemaphoreSlim.Wait fix when no timeout

See https://bugzilla.xamarin.com/show_bug.cgi?id=16267
Check for __readfsdword at configure-time

Recent versions of mingw-w64 have moved this definition to a header
included by this file, so checking simply for GCC would cause a multiple
definition error. We should instead check for this function's
availability at configure-time.

These changes are released under MIT/X11 license.
Merge pull request #813 from ColdPie1/mingw64fix

Check for __readfsdword at configure-time
Merge pull request #810 from criteo/16267-SemaphoreSlim

[Bug 16267] SemaphoreSlim.Wait fix when no timeout
Merge pull request #807 from akoeplinger/fix-fonttest

Fixed a test failure that occurs when the specified font is not installed
Remove the #error for the ARM_FPU_VFP_HARD case.
Add an IS_HARD_FLOAT macro to the ARM back end.

Also define correct values for IS_SOFT_FLOAT and IS_VFP for
the hardware floating point (ARM_FPU_VFP_HARD) case.
Expand MonoContext on ARM to hold 32 double-precision registers.

This is necessary for VFP v3 D32 systems.
Add detection of VFP v3 variants to mono-hwcap-arm.
Adjust various FP register values for hard float in mini-arm.h.
Add helper functions to the ARM back end to determine hard float and VFP registers.
Support VFP v3 variants of ARM_FLDMD and ARM_FSTMD.

Previously, we set the D bit of these instructions to Fd & 1. This
was incorrect. The D bit should only be set if we're referring to
the extra double-precision registers in VFP v3.

Take for example the instruction:

    vstmia r0, {d18-d20}

This is encoded by the GNU assembler to:

    1110 110 0 1 1 0 0 0000 0010 1011 00000110
                 |          |
                 D          Vd

The Vd is set to 2, i.e. register d2. However, we want to refer to
the d18 register, which is why the D bit is set. The CPU concats
the D bit with the four Vd bits to get 0b10010, which is 18.

However, if we do:

    vstmia r0, {d2-d4}

We get:

    1110 110 0 1 0 0 0 0000 0010 1011 00000110
                 |          |
                 D          Vd

The only difference is that the D bit is not set. This is because
the four Vd bits are enough to refer to the 16 base double-precision
registers in VFP.
Various fixes to VFP register saving in the ARM exception code.

* Adapt calls to ARM_FSTMD and ARM_FLDMD to the new D bit parameter.
* Save VFP registers based on what we detect about the hardware we
  run on, rather than basing the decision on ARM_FPU_* defines. This
  is important, because while ARM_FPU_VFP may be set, we may end up
  falling back to soft float.
* Save all 32 double-precision registers if the hardware supports
  the VFP v3 D32 variant.
* Add missing VFP register saving to mono_arm_resume_unwind ().
Add VFP register saving to trampolines.
Handle the MONO_ARM_FPU_VFP_HARD case in mono_arch_emit_setret ().
Temporary hack: Disable MANAGED_ALLOCATION since it breaks on armhf.
Implement return value passing for ARM hard float.

This is currently only for float32/float64 values. They are passed
in the d0 register. The code is a bit complicated because we only
speak float64 in the JIT, so float32 values have to be converted
to/from float64.
Print detected ARM version in configure.
Implement add_float () for hard float on ARM.