[FIX] Fix incomplete sensitivity list in SPI slave

This solves synthesis warnings.

Change-Id: I10c939a314c8cd07cbe4c316efa320a4e8ea0f17
Reviewed-on: http://brateggevoat1/gerrit/1459
Tested-by: Jenkins <jenkins@brateggevoat1.br-automation.co.at>
Reviewed-by: Thomas Mair <thomas.mair@br-automation.com>
Reviewed-by: Joerg Zelenka <joerg.zelenka@br-automation.com>
[FIX] Use falling edge of SPI select signal to reset stream protocol

Instead of the sync interrupt source, the SPI select signal (low-active)
is used to reset the stream protocol. Therefore the SPI master must hold
the SPI select signal asserted during the whole transfer!

Change-Id: I50e51bdfd5318d1f60530ecaacdd867681a2fb39
Reviewed-on: http://brateggevoat1/gerrit/1403
Tested-by: Jenkins <jenkins@brateggevoat1.br-automation.co.at>
Reviewed-by: Joerg Zelenka <joerg.zelenka@br-automation.com>
[FIX] Fix bus master being resistant to glitches

Since the acknowledge input might be a combinational path glitches are
possible. Therefore the bus master interpreter checks the acknowledge state
again before doing processing with the arrived data.

Change-Id: Ibc3e4c3d04c36feae0130c72115e221e6091dc6d
Reviewed-on: http://brateggevoat1/gerrit/1457
Tested-by: Jenkins <jenkins@brateggevoat1.br-automation.co.at>
Reviewed-by: Joerg Zelenka <joerg.zelenka@br-automation.com>
[FIX] Fix single port RAM model

- Change interface
- Replace fileio with simple RAM modeling

Change-Id: I302abe27997ded934d84443fbeda56c11f341f24
Reviewed-on: http://brateggevoat1/gerrit/1458
Tested-by: Jenkins <jenkins@brateggevoat1.br-automation.co.at>
Reviewed-by: Joerg Zelenka <joerg.zelenka@br-automation.com>
[FIX] Fix simulation warnings of some testbenches

Change-Id: Ibe09f47d2e3876e9a3b05a673971d338396fc549
Reviewed-on: http://brateggevoat1/gerrit/1460
Tested-by: Jenkins <jenkins@brateggevoat1.br-automation.co.at>
Reviewed-by: Joerg Zelenka <joerg.zelenka@br-automation.com>