Fix g_chi -omega

Per IUPAC, we should calculate peptide omega angles from
Calpha-C-N-Calpha, and there are only n-1 such angles defined for a
polypeptide of n amino acid residues.

There are some other IUPAC violations in make_chi_ind(), but solving
those is deferred to 5.0, not least because there will be a
behavioural change when we conform to IUPAC.

The problem that led to the report had several causes. The hard-coding
of the string names for hydrogen bound to peptide nitrogen (which in
CHARMM27 is "HN") meant that an H atom was not found. has_dihedral()
then checked whether a Calpha was found, which was true. Then
make_chi_ind() computed the angle based on H without doing any further
check. So some garbage coordinate was looked up when computing the
angle.

A proper fix for this kind of stuff for 5.0 requires finding all the
places we try to guess what atoms are from their names and using
properly implemented selections.

Also removed orphaned header file.

Fixes #953, details and links there

Change-Id: I63257a1d6d8ed46d251b8bc0cb308dfbd2864a97
Clarify g_gyrate -h

The description could be better still, but since I don't know
exactly what g_gyrate does, I will leave it alone.

Partial fix for #934

Change-Id: If797ed87f07d119ef5d778e341735e2c1d48ff9e
Fixed a potential race condition in tMPI_Thread_create()

The pthreads version of tMPI_Thread_create contained a potential race
condition where the tMPI_Thread_t structure may not be fully populated
as the child thread starts.

Refs #1254

Change-Id: I86e8faaa3d27b88269257be8d7df66ef728dbb0d
Make FFT detection quieter when nothing is changing

Change-Id: I58ae8571de21eb81998a6dbce5883c1343552eeb
Fix of memory leak

Fixes #1265 (probably)

freeing data in expanded ensemble code that should have been freed all along.

Change-Id: I115ee068c56e4edab8fcea828e60ee1386f00716
Code cleanup in enforced rotation module, remove warnings.

Change-Id: Iceb458b06f2c003c6325c77c3258edb112e449f6
minor function argument cleanup

Removed an unused function argument and changed anoehter one to not pass
the entire nonbonded verlet data structure to the nbnxn_cuda module, but
only what's needed from it.

Change-Id: I89699548f69245eba6d8451683ba6dc36af75dc2
Fix for a rare condition in flexible rotation potentials.

Change-Id: Icc6c7fceaba3fa53f3f2d627c3c205469fc9d710
Fix an error in selection online help.

Fixes #1262.

Change-Id: Ia9144690327b852dfab58e833cc2fdc20579b277
Fixed calculation of slab buffer size for flexible potentials.

The slab buffer size is difference in slabs between the reference and
the current positions of the rotation group. This was originally
calculated once in the init_rot_group() routine. However, it needs
to be calculated at every step since it changes when the rotation group
expands or contracts along the rotation vector.

Change-Id: I3b1fac41f88744e14e712454ae546c94f9b26750
Work around for correct treatment of all-vs-all

Neither C or accelerated all-vs-all kernels work in 4.6. The group
SIMD kernels do not work either. The non-accelerated kernel is OK,
though.

Fixes #1249 (for certain values of "fixes"), refs #1095

Change-Id: Id52c0ba110aa915e77859585c2cbfd4d529fe3ca
Fixes #1194 error reading 4.5.5 tpr files with dihres

Somehow the tpx_version produced by 4.5.5 was higher (73)
than expected, making the the tpx reading incorrectly
assuming this was using the new file format.
Now set to the version before the
first official 4.6 tpx format, 82 to match the tpr files
in the regression tests. Duh!

Change-Id: I40d8ffa0d350cf3b690f8dfb071fc191f027d02f
Fixing the constraint dhdl term in shake

Addresses and corrects new issues with #1255,
with additional comments explaining what else
may need to be done in the future to make sure
that the theory of the changes are completely
correctly founded.  See the redmine entry #1255
to see the numerical validation of the current choices.
Also adds possible missing constraint dHdl contribution.
Fixes #1268

Change-Id: Ibe3980c2e265cced49b03b966e02143c5cf9f07c
fix thread offset + stride check

This commit fixes the check which makes sure that the combination of
thread offset and stride does not cause pinning beyond the last hardware
thread.

Additionally, also improved pinning-related warnings and notes.

Change-Id: Ia33610cacb7526dca2ff69491aac2973c7333022
Added GROMOS96 54A7 force field files.

Files are taken from ATB, which is hosted by Alan Mark, who
was an author on the GROMACS96 54A7 paper, which is cited in
forcefields.doc. So these files are effectively equivalent to
the reference implementation.

Fixes #773.

Change-Id: I800da3d3535a09cd5beb7f2b4d1b42422cc4329f
add workaround for clang on AMD with FMA

The clang bug which causes incorrect code to be generated on AMD
with FMA (Piledriver and Bulldozer) is in fact caused by an assembler
bug and can be worked around by switching to an external assembler.
This commit implements such the workaround for clang 3.1 and 3.2.
The bug was fix in clang version 3.2-svn-r173176:
http://llvm.org/bugs/show_bug.cgi?id=15040
Hence, no workaround is needed for clang 3.3 with AVX_128_FMA
acceleration.

This workaround is ineffective on Mac OS because there is no suitable
external assembler, but distinguishing between vanilla and Apple clang
requires more code than what's worth adding to cover the case of
AMD-based Hackintoshes (all Mac-s are Intel-based).

It is appropriate to amend only C and not C++ compilation for
release-4-6 branch, but when merging this to master branch, reconsider
the detail of the implementation.

Refs #1099

Change-Id: I835e0f2436ee33507514d3bc3980fcc227e2e36f
fix thread-safety issue in affinity layout detection

The pinning stride variable is shared by thread_mpi ranks and its
value is changed only when its initial value is 0. This posed a
thread-safety issue and in some cases the selected pinning stride was
only reported in the log if rank 0 happened to arrive first to the
affinity layout detection.

Refs #1254

Change-Id: Id32af8cbeacea2205fd15c30b46320ec7dd35e5e
fix unnecessary switch to polling GPU wait

Commit 84597ae introduced an incorrect condition for testing
whether mdrun should and can switch to polling GPU wait.
This minor bug results in swithching to polling wait even when this
is unnecessary (i.e. when the driver in use is >=v5.0), This is
rather harmless, but the polling wait is fragile, so we should use
it only when really necessary.

This commit fixes the switching as well as reorganizes the conditionals
to make it more clear that switching is needed when ECC is on and the 
NVIDIA GPU driver is older than v5.0.

Change-Id: I9106cb34c9a8fde2f9b54045d9b03ee5f5d50d8b
New patch release 4.6.2

Added details of Pronk, et al 2013 paper to README

Bumped version to 4.6.3-dev. The v4.6.2 tag points to the actual
version that built the tarball, which was patch set 1.

Change-Id: I9b17cd80f34e2d175dbed0d87677a0611254b7c7
Merge branch 'release-4-6' into master

Mostly easy. selhelp.cpp got the fix from selhelp.c

Omitted the content of 34a402e7 (clang-AMD-FMA work-around) in favour
of reworking it for C++ in a child patch

    Conflicts:
        CMakeLists.txt - kept master version number!
        src/gmxlib/selection/selhelp.c - deleted
        src/gromacs/gmxana/pp2shift.h - deleted
        src/gromacs/legacyheaders/pull_rotation.h

Change-Id: Ibf0c9af136e39dfcbef0a85eb7d314740706cb60