System as used for initial PICA bench test

added the signal vdif_AUXTIME_p/n
System as used for initial PICA bench test

added the port AUXTIME_p/n
System as used for initial PICA bench test

added AUXTIME
added PPS_PIC_p/n signals
drive DAC_CLK with adc_clk
drive PPS_PIC_sig with test_ctr(0) for a test source on backplane connector
drive DAC bits with test_ctr(7 downto 4)
change inputs to test point muxes to include all differential inputs in motherboard connector
drive test point muxes from C167_reg1 and C167_reg2
drive all ROUTB test points.  ROUTB(3) gets copy of 125 MHz clock for in-system test
drive test_ctr_fifo with 125 MHz system clock as an alternate test of 125 MHz.
System as used for initial PICA bench test

add AUXTIME