wb_sdram_ctrl: Fix write and burst cache refill clash

If a write would occur during a burst cache refill and
the write address have not yet been refilled, the
burst cache value would be the one prior to the write.
To fix this, the write is held off until the refill
to that particular address have finished and then do the
write to both the burst cache and the actual memory.
atlys: only compile unisim libs, not all
atlys: remove nonexisting ddr2 sync funtions from eth_stim
atlys: rename ps2_wishbone to ps2_wb
add mor1kx to simulation Makefile
add mor1kx_monitor
de0 nano: fixes for dbus arbiter

Stop the case where a new access to a different slave causing a single cycle of cyc/stb assertion to the previous slave.
de2_115, de0_nano: phase shift sdram clock

This was suggested by vitorqa on the opencores forums [1]
as a solution for a problem another user had.
As he claims in his post, the Using_the_SDRAM [2]
document from altera suggests shifting the sdram clock
a necessity as well.

I've tested this on the de0 nano and it works fine.

[1] http://opencores.org/forum,OpenRISC,0,5024
[2] ftp://ftp.altera.com/up/pub/Altera_Material/11.0/Tutorials/Verilog/DE0-Nano/Using_the_SDRAM.pdf
wb_sdram_ctrl/arbiter: use wb_clk for buffer cache writes

All signals in this block is in the wb_clk domain,
so clocking them with sdram_clk is clearly a mistake.
memtest-BigArray.c added, which write to a big array and verify data.
dbus arbitor match width changed (8->6), because 64M SDRAM uses 26-bit address.
Merge remote-tracking branch 'remotes/origin/master'