OMAP3+: Smartreflex: Fix interrupt disable sequence

With the current interrupt disable sequence, we disable IRQENABLE
followed by clearing of IRQSTATUS. With this sequence, we see, at
times CORE domain does not hit OFF mode during cold boot because
SR modules(Core/IVA/MPU domains) are stuck 'in transition'.

After the IRQ is cleared by writing the SR_xxx_IRQENABLE_CLR ,
the SW cannot read the interrupt status from IRQSTATUS register.
SW should have cleared all IRQ completely before disabling the
module. If the SW disable the module by the MODULEMODE bit
before clearing the IRQ status, the SR module is still in the
'In transition' mode.

Hence, the right sequence we have is write to IRQSTATUS register
to clear the interrupt, then write to IRQENABLE_CLR register to
disable the interrupt to ensure that no pending interrupts exist
in the system on disable of SmartReflex AVS block.

Change-Id: Ic0e3d9960ed9511769c3c25b2c71ff1e53bcc796
Reported-by: Honda Kenji <x0092217@ti.com>
Reported-by: Maki Tanaka <m-tanaka1@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Huzefa Kankroliwala <huzefank@ti.com>
OMAP3+: Smartreflex: fix interrupt status clear write

ChangeId Ic0e3d9960ed9511769c3c25b2c71ff1e53bcc796
(OMAP3+: Smartreflex: Fix interrupt disable sequence)
intended to write the interrupt mask to status register
prior to disabling it, instead, we ended up writing 0
to the register, essentially leaving the interrupt status
not cleared. Fix this by splitting the interrupt disable
sequence out(v1 and v2 require different operation) and
ensure we write the correct value to interrupt status register.

Change-Id: Ib28352ff9ea4ec4b787aeee14a907e73080a6d12
Signed-off-by: Nishanth Menon <nm@ti.com>