defconfig: update
tegra: lower G min and touch floor min
[PATCH] Restrict slave mountspace so Dalvik apps can mount
 system-wide volumes

Android 4.2 implements multi-user storage using per-process mount
namespaces.  Everything under "/" (the entire filesystem hierarchy) is
marked as a recursive-slave mountspace for all zygote instances.  This is
done so that user-storage sandbox mounts under /storage/emulated are hidden
from other apps and users.

Unfortunately this means that any Dalvik app (actually, any program whose
clone/fork ancestry includes a Dalvik zygote, which is everything except
services spawned directly from init) cannot mount system-wide volumes.
Thus, apps like CifsManager are effectively broken in Android 4.2, since
its cifs mounts are only visible to the CifsManager app itself.  All other
apps see empty mountpoints instead of the mounted volume.  Furthermore,
Linux provides no provision for a process to "escape" a recursive-slave
mountspace in versions prior to Linux 3.8 (setns syscall).

Here, we restrict rootfs-slave calls to /storage (and, due to a possible
kernel bug, /mnt/shell/emulated) so that Dalvik apps can mount system-wide
volumes elsewhere (with appropriate permission, as in earlier versions of
Android), while retaining full multi-user storage compatibility.  It is
made available as a kernel-based workaround for instances where libdvm can
not be modified.

This change requires that a tmpfs volume is mounted as /storage in init.rc.
If this volume is unavailable, then we falls back to the previous behavior
of marking the entire filesystem hierarchy as slave.
Revert "[PATCH] Restrict slave mountspace so Dalvik apps can mount"

This reverts commit 917259881256aaed1b78cf9d844f93ac5aba4874.
Remove 1.9GHz as pll_x was being capped at 1.7GHz anyway. Need to look into later.
block: Add support for reinsert a dispatched req

Add support for reinserting a dispatched request back to the
scheduler's internal data structures.
This capability is used by the device driver when it chooses to
interrupt the current request transmission and execute another (more
urgent) pending request. For example: interrupting long write in order
to handle pending read. The device driver re-inserts the
remaining write request back to the scheduler, to be rescheduled
for transmission later on.

Add API for verifying whether the current scheduler
supports reinserting requests mechanism. If reinsert mechanism isn't
supported by the scheduler, this code path will never be activated.

Signed-off-by: Tatyana Brokhman <tlinder@codeaurora.org>

Conflicts:

	include/linux/elevator.h
block: Add API for urgent request handling

This patch add support in block & elevator layers for handling
urgent requests. The decision if a request is urgent or not is taken
by the scheduler. Urgent request notification is passed to the underlying
block device driver (eMMC for example). Block device driver may decide to
interrupt the currently running low priority request to serve the new
urgent request. By doing so READ latency is greatly reduced in read&write
collision scenarios.

Note that if the current scheduler doesn't implement the urgent request
mechanism, this code path is never activated.

Signed-off-by: Tatyana Brokhman <tlinder@codeaurora.org>

Conflicts:

	include/linux/elevator.h
row: Adding support for reinsert already dispatched req

Add support for reinserting already dispatched request back to the
schedulers internal data structures.
The request will be reinserted back to the queue (head) it was
dispatched from as if it was never dispatched.

Signed-off-by: Tatyana Brokhman <tlinder@codeaurora.org>
row: Add support for urgent request handling

This patch add support for handling urgent requests.
ROW queue can be marked as "urgent". If an urgent queue was
un-served in a previous dispatch cycle and a request was added
to it - it will trigger issuing urgent request to the device driver.

Signed-off-by: Tatyana Brokhman <tlinder@codeaurora.org>
block: fixes required to make the kernel compile with ROW.

Signed-off-by: franciscofranco <franciscofranco.1990@gmail.com>
cpufreq: interactive: update and tweak
arm: tegra: Set Core to 0.95V in LP1

When the device prepares for LP1, the Core voltage is set to the
highest value(1.2V for Enterprise and Kai, and 1.3V for AP37 and
Cardhu). This is to set for some of the driver suspend along the
sequence need a higher emc frequency and thus a higher Core voltage.

Since the sequence of drivers suspend depends on the sequence of
their registration in the table, which in turn is platform-dependent,
there is no right place in the LP1 entry path where the Core voltage
can be set to a lower voltage. Hence, the Core voltage remains high
in LP1 resulting in higher power.

Thus, the only safe location where the Core voltage can be lowered is
once all the drivers are suspended and the DRAM is set in self-refresh,
at the final point just before the system is suspended in the IRAM code.
This location at the assembly code ensures that no other module will be
running and thus that nothing will require a higher core voltage. The Core
is set to the lowest possible value since nothing requires it. It is then
restored to the highest voltage as soon as the LP1 resume code is started
so that all drivers are resumed safely.

At the execution point in IRAM during LP1 suspend path, even the I2C clocks
are gated. They must be reset first and then the I2C transaction is performed.
An I2C transaction involves 4 bytes of data, to send the slave address,
the Core voltage register address and 2 bytes of data which has the value
to set the voltage(the second byte is not required for this transaction).
Once these registers are set, the I2C transaction is performed by setting
the I2C transaction register to 0xA02. After sending the I2C transaction,
we wait for about 250us to check the status of the transaction and if not
updated, wait for more time to check again. If after 2ms and the transaction
fails to register, the transaction is aborted and the device is allowed
to enter at high voltage. Since the failure rate of I2C transaction is very
low at this point in execution where there will be no conflicts in the bus,
it is okay to have Core high for some of the LP1 cycles.

However, it is unacceptable for the I2C transaction to fail on the way
from LP1 resume since the device cannot come up with a lower Core
voltage. In this case, the transaction is retried again and again till
it is successful. There is no way but to keep trying as the device
would fail to resume with Core at 0.95V.

Each platform(or each PMU) has different values for the I2C transaction
ie. slave address, Core voltage register and the value to set the
voltage. For the device in IRAM, it cannot access anything in SDRAM
memory, these values needs to be pushed to IRAM memory before the device
starts execution in IRAM. This is done during initialization of suspend
code when it picks values from the board files and copies it to IRAM
part of code, before the whole memory is copied to IRAM.

This new feature is controlled by a KConfig variable TEGRA_LP1_950 which
should be enabled once the board file of the device is updated with the
right values. The device hangs when it does not have the right values for
the I2C transaction.

With this change in Core, LP1 power is reduced by 12mW in Enterprise,
20mW in AP37 and about 24mW in Kai.

Bug 1035684

Change-Id: I4318c66fd70ab227ef0786d6a13286e020e4541d
Signed-off-by: Karthik Ramakrishnan <karthikr@nvidia.com>
(cherry picked from commit ab476f287376fd0ae51a9f298659f5eba19f0296)
Reviewed-on: http://git-master/r/124779
Reviewed-by: Lokesh Pathak <lpathak@nvidia.com>
Tested-by: Lokesh Pathak <lpathak@nvidia.com>
adapted to use for Nexus Grouper from NV reference

Signed-off-by: faux123 <reioux@gmail.com>

Conflicts:

	arch/arm/mach-tegra/Kconfig
arm: tegra: Board files settings for LP1 0.95V CoreV

Set the register values for each of the board files to
keep the Core voltage to 0.95V in LP1.

This change is only for those platforms where LP1 is supported.
Enterprise and Kai are the main platforms for this change. There
is no support for Cardhu for LP1 and so is left blank and the
feature will be skipped for Cardhu platforms, except for AP37.
AP37 with a PM269 board needs this change and so Cardhu board
file is updated with the values specific to AP37.

This change is part of the feature to set VCore to 0.95V
Refer to http://git-master/r/124135 for more details
Bug 1035684

Change-Id: I6d1d984b0e7968b441cebbc37705c25647a4a85a
Signed-off-by: Karthik Ramakrishnan <karthikr@nvidia.com>
(cherry picked from commit b46921e475bd95e729896a6763bc94df1e03ee4a)
Reviewed-on: http://git-master/r/124780
Reviewed-by: Lokesh Pathak <lpathak@nvidia.com>
Tested-by: Lokesh Pathak <lpathak@nvidia.com>
adapted for use on Grouper from NV reference

Signed-off-by: faux123 <reioux@gmail.com>
Revert "Revert "ARM: tegra: clock: Increase boost_up_threshold for AVP clock""

This reverts commit 55c5d9c1cb6155224ffb52b14d7df61acc3d68fc.
mach-tegra: cpuquiet.c: tweak delays
defconfig: update
Merge remote-tracking branch 'upstream/alpha2' into alpha-mr1