initial commit of code

note that the IP cores had to be tweaked a bit, beyond the standard
generation that would seem to be indicated by the inclusion of just
.xci files. In particular, the MIG-generated DDR3 core has some bugs
where the single-ended input clock isn't properly generated (it
insists on making it differential from the pads). You will have
to edit the infrastructure block to remove the generate statement
and replace the ibufg with a wire (not a bufg) to get the block
to work.