Change CacheRead operation to use data_addr for dram_pending.

Previously, the CACHE_READ operation used the cache page address to track
reads to DRAM. This meant that only one read per page could go out at
a time. Since the fastmem microbenchmark demonstrated that this caused
a major bottleneck in streaming reads (HybridSim achieving ~3.35 GB/s
while DRAMSim was capable of 8.35 GB/s), we want to be able to send
multiple DRAM reads out to DRAMSim concurrently. We accomplish this
by changing the CACHE_READ operation to use the data_addr (the actual
64-byte granularity address that will be sent to DRAMSim to get the data
requested by the external access) in the dram_pending table.

However, since VICTIM_READ still uses the page address to track a large
number of accesses (one for each 64-byte location within a flash page),
this meant that DRAMReadCallback needs to know which address to use (the
data_addr or the cache page address). To determine this, we simply have
it look in the dram_pending_wait map and see if an entry for the current
page exists. If so, then it must be a VICTIM_READ and we use the cache
page address. Otherwise, it must be a CACHE_READ and we use the data_addr.

These changes also depend on the previous commits that implemented locking
at a finer grained level and moved the wait set to dram_pending_wait.

This commit also contains a minor fix in which debug output was not
properly guarded by DEBUG_CACHE.

Also added a new trace file (traces/no_delay_test.txt) to test accessing
multiple locations within a page concurrently.