FogBugz #169918: Map the OCRAM in the device tree file.

By mapping the OCRAM in the device tree, this enables peripheral(s) to make
use of the OCRAM by a assigning an iram node, and using:

of_get_named_gen_pool(np, "iram", 0);

This patch also enables the generic SRAM driver that will map the OCRAM into
a generic mempool.

Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
---
v3: fix-up drivers/misc/Kconfig to match kernel.org
v2: 64kB of OCRAM
FogBugz #171612: Remove hard-coded frequencies for Timers and UARTs

Update the UART and timers clock node so that the driver can query for the
frequency, instead of hard-coding the frequency values.

Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
GCOV fix for GCC 4.7.x

Changes the data structures of GCOV to handle GCC 4.7 code

Signed-off-by: Yves Vandervennet <yvanderv@altera.com>
This patch adds to support burst mode for dev-to-mem and mem-to-dev transmit

Change-Id: I9723e49383416773699cf7735168177c8d036f30
Signed-off-by: Boojin Kim <boojin.kim@samsung.com>
Signed-off-by: Graham Moore <grmoore@altera.com>
FogBugz #169570: TX TCP Checksum offload is broken for Jumbo frames

The Synopsys EMAC will checksum jumbo transmit frames only up to a
certain size correctly, since the controller will start to egress
an outbound packet when it starts reaching the maximum size of the
transmit fifo. In the Altera configuration case, the PBL, or
programmed burst length is set to 64, the transmit fifo size is 4K,
and the bus datawidth is 32-bits. The equation to determine the
correct maximum MTU is FIFOSIZE-((PBL+3)*(BUSWIDTH/8)) ==
4096-(67*4) = 3828. Then we need to account for possible VLAN tags,
inner and outer, and then transform than number into an Ethernet
MTU, which gives us 3828-8-14-4 (8 bytes for two VLANs, 14 bytes
for the standard Ethernet header size, and another 4 bytes for
CRC). That gives us 3802. So we'll make it a maximum jumbo frame
size of 3800.

Signed-off-by: Vince Bridgers <vbridger@altera.com>
FogBugz #171833: Strip VLAN tags in EMAC Receive path so GRO works as expected

The EMAC driver was advertising the NETIF_F_HW_VLAN_TAG_RX feature flag,
which indicates that the hardware supports VLAN tag stripping in receive
frames, but the hardware does not support VLAN tag stripping, and the
driver was not stripping the VLANs either. This causes a slow processing
path to be taken in the GRO portion of the stack's receive processing,
drastically impacting receive performance. The fix is for the driver to
detect and strip the VLAN tag correctly, and correctly setting any
detected and received VLAN tag into the skb.

Signed-off-by: Vince Bridgers <vbridger@altera.com>
FogBugz #168684: Disable NAND driver in devicetree

On our CycloneV, sometimes a NAND chip is detected even though
there isn't one on the board.  The Denali NAND driver already
has code to prevent erroneous detections, but apparently it's
not working as well as it could.  Our solution is to disable the NAND
driver by default for socfpga.

Signed-off-by: Graham Moore <grmoore@altera.com>