msm: spm-v2: Add support for AVS

Changing the voltage with the AVS feature enabled requires
certain care. First, temporarily disable AVS before writing any
registers which would change the voltage. Then kick the PMIC
state machine back to the idle state so that our write to the
VCTL register takes effect immediately. We don't need to check
the state machine for idle, instead we should just confirm that
the SPM has sent the voltage we wanted to send and then we can
program AVS to allow up to 4 12.5mV steps down from the voltage
programmed in VCTL. Once this is all done reenable AVS so that
the voltage can be decreased after the AVS_DELAY counts down.

Change-Id: I1c23fd0549e401152fd16de9032ceaf7c3e067c4
Signed-off-by: Praveen Chidambaram <pchidamb@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Anji Jonnala <anjir@codeaurora.org>
msm: spm-v2: Disable AVS operations on unsupported targets

Do not enable/disable AVS on targets where it is not enabled at boot.
Enabling it on targets when AVS isn't enabled and the AVS control
parameters aren't configured, causes undefined behavior and random
crashes.

Change-Id: Id0c4e10618437eed1b383145a6a4f25bbd901647
Signed-off-by: Anji Jonnala <anjir@codeaurora.org>
msm: Remove incorrect SAW2 PMIC DATA commands

SAW v2.2 does not support PMIC_DLY. Remove the incorrect mapping in the
probe method. Also, PMIC_DATA0 is used by L2 SPM for enabling the S5
gang in SAW v2.2. Using this to buffer the S5 gang voltage is
unnecessary and incorrect.

Signed-off-by: Praveen Chidambaram <pchidamb@codeaurora.org>
(cherry picked from commit 2772d83b3a783d1de5ef52c3d276b3572238309f)

Change-Id: Ia7c928259dd57b2905ede182157d0adafc8dfad7
Signed-off-by: Sudhir Sharma <sudsha@codeaurora.org>
msm: spm: Add cross-calling support to change voltages

SPM block is responsible for power collapsing the core, but also
interacts with the PMIC through hardware to change core voltage. It
would be beneficial to frequency algorithms to change frequencies and
thereby voltages of all cores running from a single core. In some
targets, the SPM is configured to set voltage only for that core. Ensure
that the core voltage is set only from that core.

Change-Id: I656e20a49d9784f08e9ce4d4e8f6c15760ba015b
Signed-off-by: Praveen Chidambaram <pchidamb@codeaurora.org>
(cherry picked from commit bcd483b93abd434d0207211c8bab7d0f7d653c27)
(cherry picked from commit 740945d7d0d4bab1d3d7674e7061fbe0acfe0d19)
msm: spm_devices: Fix failure to set vdd during cpu_up

To avoid a core vdd being set when the core could be executing the SPM
finite state machine, set the call to set vdd to execute on that
particular core using smp_call_function_single(). However, the call can
only be executed on a core thats online.

When a core is brought online, the acpuclk driver needs to ensure that
the core vdd is set correctly before the core can be brought online.
But, since smp_call_function_single() works on cores that are online,
the call to set vdd will fail and therefore the core will cannot be
onlined.

The error that would be seen when the kernel command line parameters has
maxcpus=2

[244.759529] saw_set_voltage: 8821_s0: msm_spm_set_vdd failed -6
[244.764687] acpuclk-8064 acpuclk-8064: regulator_set_voltage(krait2)(-6)
[244.771463] _cpu_up: attempt to bring up CPU 2 failed

It is safe to do a set the vdd of an offline core when called at cpu_up,
so bypass smp_call_function_single() and set the voltage of the core
directly from cpu0.

This chicken and egg problem will not be seen if the cores were
initialized by calling boot_secondary() at init.

CRs-fixed: 407553
Change-Id: Ifdc9a645b5a9715d0fda065b4b0c2bab056a3ade
Signed-off-by: Praveen Chidambaram <pchidamb@codeaurora.org>
(cherry picked from commit 8624ce7c52bba5acf7a2321690def8c732680199)

Signed-off-by: Dhivya Subramanian <dthiru@codeaurora.org>
msm: spm: set vdd directly for current cpu

In cases where a cpu is setting vdd for itself we need not
call msm_spm_smp_set_vdd through smp_call_function_single.

Without this change when CPU calls for itself when interrupts
are disabled we get following warning

[ 38.407752] ------------[ cut here ]------------
[ 38.407752] WARNING: at kernel/kernel/smp.c:320
smp_call_function_single+0xa8/0x1c8()
[ 38.407752] Modules linked in: adsprpc
[ 38.407752] [<c00149b8>] (unwind_backtrace+0x0/0x11c) from [<c0082afc>]
(warn_slowpath_common+0x4c/0x64)
[ 38.407752] [<c0082afc>] (warn_slowpath_common+0x4c/0x64) from
[<c0082b2c>] (warn_slowpath_null+0x18/0x1c)
[ 38.407752] [<c0082b2c>] (warn_slowpath_null+0x18/0x1c) from
[<c00c510c>] (smp_call_function_single+0xa8/0x1c8)
[ 38.407752] [<c00c510c>] (smp_call_function_single+0xa8/0x1c8) from
[<c0058f6c>] (msm_spm_set_vdd+0x48/0x70)
[ 38.407752] [<c0058f6c>] (msm_spm_set_vdd+0x48/0x70) from [<c0056a98>]
(msm_pm_power_collapse+0x13c/0x334)
[ 38.407752] [<c0056a98>] (msm_pm_power_collapse+0x13c/0x334) from
[<c0057120>] (msm_pm_enter+0x170/0x2dc)
[ 38.407752] [<c0057120>] (msm_pm_enter+0x170/0x2dc) from [<c00b7580>]
(suspend_devices_and_enter+0x1d0/0x334)
[ 38.407752] [<c00b7580>] (suspend_devices_and_enter+0x1d0/0x334) from
[<c00b7800>] (pm_suspend+0x11c/0x1f8)
[ 38.407752] [<c00b7800>] (pm_suspend+0x11c/0x1f8) from [<c00b87a4>]
(suspend+0x68/0x180)
[ 38.407752] [<c00b87a4>] (suspend+0x68/0x180) from [<c009b050>]
(process_one_work+0x280/0x488)
[ 38.407752] [<c009b050>] (process_one_work+0x280/0x488) from
[<c009b46c>] (worker_thread+0x214/0x3b4)
[ 38.407752] [<c009b46c>] (worker_thread+0x214/0x3b4) from [<c009f364>]
(kthread+0x84/0x90)
[ 38.407752] [<c009f364>] (kthread+0x84/0x90) from [<c000f108>]
(kernel_thread_exit+0x0/0x8)
[ 38.407752] ---[ end trace da227214a82491ba ]---

Change-Id: I1aa121f57d74860b6bc8620b40699567e55a9d02
CRs-Fixed: 480408
Signed-off-by: Venkat Devarasetty <vdevaras@codeaurora.org>
msm: avs: Remove vestigial software based AVS

Older targets like 8x50 had the first version of Apdaptive Voltage
Scaling done in software. This feature was never enabled and supported.
Remove the code and the associated config items.

Change-Id: If3bdab7d0bdb5d51e099f7c37f56592826edc102
Signed-off-by: Praveen Chidambaram <pchidamb@codeaurora.org>
(cherry picked from commit 4ca77687eba64b56426b51f9e0edd9fede7d389f)
msm: AVS: Refactor and clean up avs_hw.S to avs.c

Refactor AVS API to a cleaner C implementation. The new implementation
uses C assembly functions and provides a cleaner way for future targets
to add new AVS functionality.

Also fixed a possible issue with the earlier AVS_ENABLE and AVS_DISABLE
implementations. The earlier implementation did a get_cpu() and compared
it against the cpu for which AVS was to to be disabled, if the cpu's did
not match then it did not return an error and avs could have been left
enabled during the voltage change. In this new implementation, enable
and disable use smp_call_function_single() to ensure that the enable and
disable indeed happen on the core requested.

If acpuclock_set_rate() was called on the right core correctly during
cpufreq frequency change, there would have been no issue, but newer
implementation of mach-msm/cpufreq.c does not gaurantee that.

Change-Id: I94db3fc70341ceb79d747d54c7f525056b377755
Signed-off-by: Praveen Chidambaram <pchidamb@codeaurora.org>
(cherry picked from commit 5e6141182f2a3638aaa04ed399643c013e414a65)
msm: avs: Restore core voltage when disabling AVS

AVS changes the core voltage to match the current operating conditions
on the part. Not all frequencies supported by the target have characterized
AVS delay synthesizer (AVSDSCR) values. For frequencies that do not have
AVSDSCR set, AVS is not enabled and so need to operate at the
characterized voltage for that frequency. Disabling AVS does not
however, restore the operating voltage to the value the rail was
configured to. This may cause frequencies that do not have AVSDSCR to
run at lower voltage than prescibed.
Set up the core voltage back to the last known good value when disabling
AVS.

Change-Id: I5389996288fa49e45c469d2a8917e00900261de7
CRs-fixed: 457772
Signed-off-by: Praveen Chidambaram <pchidamb@codeaurora.org>
Signed-off-by: Anji Jonnala <anjir@codeaurora.org>

Conflicts:
	arch/arm/mach-msm/spm_devices.c
msm: lpm: lpm resources bug fixes

Bug fixes to get RPM assisted power collapse working.
Unstable behavior was seen because L2 SPM state wasn't
being reset as part of exiting power collapse.
RPM driver callbacks were being missed because the
resource type comparison from the callback with the
resource type maintained at lpm_resources was failing
due to endian related issues.RPM sleep set processing
fails because vdd-dig resource doesn't use absolute
voltage values but voltage corner values.

Change-Id: I5b7218ba87574f2e7296378ded5e86fcac085203
Signed-off-by: Girish Mahadevan <girishm@codeaurora.org>
msm: rpm-smd: call SMD API to mask/unmask SMD interrupt.

When the system goes to sleep, the power management code sends a sleep
set to RPM. The code executes with interrupts disabled so the power
management code polls for ack message from RPM. Since the SMD interrupt
is in a triggered state and irq handler hasn't had a chance to run, the
pending interrupt prevent the Core from entering a low power mode.

To prevent interrupt from waking the system up, disable/enable the RPM to
SMD interrupt while entering/exiting sleep mode, by calling into the SMD
API.

Change-Id: I38faa18e6b1d7f4cc92d72c3da4ac8ca29275444
Signed-off-by: Mahesh Sivasubramanian <msivasub@codeaurora.org>