Initial support for the L2 Cache Controller PL310.
Improve L2 support in Bus DMA, add ARM TEX defines.
We already have DSB.
If a device exists but is not found, do not crash

Cleanly ignore the device and continue booting.
Initial attempt to make a commonized arm L2 controller for cortex

NOTE: due to omap non-priv state and needing secure writes to
modify L2 registers, the driver is temporarily hacked up a bit.

Create an API for the L2 enable/debug operations.

Do not flush L2 before enabled.

Use common l2 driver for imx

disable L2 on beagle until it is debugged.
Improve MPCore Interrupt Controller and Global Timer to have commonized ARM Cortex drivers.
Adapt beagle to new cortex bus.
divide clock rate by 1000 for print, not 1024
remove unused device addresses (now cortex devices)