Function declarations in packages

This is still basic. Definitions are still not done.
Basic structure for emitting packages.
Fix dump of primitive CHARACTER types.
Rework scope types and constants so we can tell imported from local names.

The package emit of types and constants needs to know which names are
from the current type and which are imported from libraries. Rework
the scope handling of those names so that the information is preserved.
Implement subprogram bodies in package bodies.
Fix SV emit of ForLoopStatement and ReturnStmt.
SV emit function ports in package subprograms.
Add support for SystemVerilog return statements.
Use $ivl_unsigned to implement VHDL to_unsigned function.

The VHDL to_unsigned function with to arguments is best handled
in the ivl elaborator, so have it generate an $ivlh_to_unsigned
function call in the vhdlpp code, and implement it in the ivl
core.

Also, implement the 'length attribute as a $bits() call for
similar reasons.
Don't crash if function is not found.
Lexor detects that excaped identifiers may be package names.
Handle constant functions from other scopes, i.e. packages.
Fix evaluation wrong expression for const >= expressions.
Fix repeated use of disabled const functions.

If constant functions are exited by a return/disable, fix
the leaked "disable" flag that causes blocks in the next
try at the function to not work.

There are also a lot of debug messages added to help find
this and similar problems.
Support compile-time evaluation of named blocks.
Handle rising_edge and falling_edge functions.
Some shorthand type marks in write_to_stream.
Elaborate VHDL entity port types/expressions.

We need to elaborate expressions so that function calls in
expressions (i.e. ranges) get bound to their proper scope.
This binding is in turn used to emit package scopes. This
is particularly interesting for ports of entities.
Do a better job of figuring the vtype of an expression.
Parse (to sorry messages) unbounded array definitions.