Makefile: Set for build

Signed-off-by: Amperific <amperific@gmail.com>
Revert "different dirty ratios behavior for screen-on / screen-off"

This reverts commit a5565f51e76f99474b4c832d0f3182a512894471.
Revert "Tweak deadline and sio"

This reverts commit 43e99b9258dff360ac4d4c8dddf20a034184c219.
OMAP4: PM: OPP/Clock: Add virtual clocks for high IVA OPPs support

To get correct frequencies for IVA OPP higher than OPP100
IVA DPLL should be reconfigured.
Tesla is also supplied from the same IVA DPLL, so frequency on DSP
should be reconfigured together with IVAHD frequency.

This is achieved by adding virtual clocks for IVA and DSP.
Main logic is implemented in IVA virtual clock which sets
frequency for both IVAHD and DSP.
DSP virtual clock is just a dummy clock and it do nothing.

Necessary DSP OPP is set via IVA virtual clock by using DVFS framework feature:
if device on which OPP is set is not the primary device in voltage domain,
then constraint to the same OPP is set for primary device.
In case of DSP the primary device is IVAHD.

If switching to the lower OPP will cause IVA DPLL scaling up,
then frequency of IVA and DSP should be scaled down before DPLL.

Change-Id: I1b229f1d52f0f8bfa4f65f08221df1e1ba6194bc
[jagadeeshwar.reddy@ti.com: original patch author for 4430]
Signed-off-by: Jagadeeshwar Reddy <jagadeeshwar.reddy@ti.com>
[taras@ti.com: modified and extended for all OMAP44xx]
Signed-off-by: Taras Kondratiuk <taras@ti.com>

Conflicts:
	arch/arm/mach-omap2/opp4xxx_data.c
OMAP: clock: Add dummy round_rate and set_rate functions

Add functions which are going to be used by dummy virtual clocks:
long clk_dummy_round_rate(struct clk *clk, unsigned long rate)
int clk_dummy_set_rate(struct clk *clk, unsigned long rate)

Change-Id: I9bb1e886888a117548d62ef2edd9598bce2723e6
Signed-off-by: Taras Kondratiuk <taras@ti.com>
OMAP4: clock: Add 'virt_lcd_pclk' clock

Add virtual LCD pixel clock which is going to be used for DSS OPPs

Change-Id: Ia42668873d4dbe75deef22e97cec449a00f987d0
Signed-off-by: Vitaly Chernooky <vitaly.chernooky@ti.com>
Signed-off-by: Taras Kondratiuk <taras@ti.com>
OMAP4: OPP: Add DSS OPPs

To generate pixel clock rate higher than 93MHz
DSS has to scale VDD_CORE to at least OPP100 level.

This patch adds two DSS OPPs, for DSS to be able
to control minimum VDD_CORE level.

Change-Id: I98eab1c3b56fcf41026b742cb43c8155b68dd5c4
Signed-off-by: Taras Kondratiuk <taras@ti.com>

Conflicts:
	arch/arm/mach-omap2/opp4xxx_data.c
OMAPDSS: DSS: Scale DSS OPP according to pixel clock rate

Before enabling pixel clock DSS should set its OPP
for OPP framework to set correct VDD_CORE voltage level.

When pixel clock is disabled DSS can set the lowest OPP.

Change-Id: Ia1459614ae306dba9b048b149e474442e2880bba
Signed-off-by: Taras Kondratiuk <taras@ti.com>

Conflicts:
	drivers/video/omap2/dss/dsi.c
OMAP4460: TWL/TPS data: update retention voltages to spec rev 0.3

Update retention voltages from Operating Conditions Data Manual
Addendum Revision 0.3 (August 2011).

OFF voltage is also updated as per requirement of 4460 OFF mode
conditions.

Change-Id: I558f0a483911b2616d0a19f9272a03258e35904a
Signed-off-by: Nishanth Menon <nm@ti.com>

Conflicts:
	arch/arm/mach-omap2/omap_twl.c
OMAPDSS: DISPC: Pipe threshold sizes power optimization.

This patch changes the calculation of thresholds and sets low
threshold to half of buffer size for OMAP4. The memory will
able to sleep between transactions to dss because dss will
read by big chunks.

boype: Also removed dispc_calculate_threshold function, as it is no longer used.

Backport from TI omapzoom kernel 3.4 repo, based upon:
http://git.omapzoom.org/?p=kernel/omap.git;a=commit;h=cd99eb345e1ad26ffbc665f46ea917dad762937b
page_alloc.c: Tweak the min_free_kbytes to 8192

Signed-off-by: Amperific <amperific@gmail.com>