Replaced ccu_clk_uldiv code from sun4i's include/mach/aw_ccu.h
The sun7i ccu_clk_uldiv doesn't behave the same as the sun4i and
sun5i versions.  It rounds *up* (adds 1 to dividend if the remainder
is non-zero); whereas the sun4/5i performs simple 64-bit integer
division, i.e., they round down.  This causes clocks to be set
differently on the sun7i if the PLL's clock can't be evenly divided
by whatever divisor is passed by the calling code.
sunxi:cedar Clean up video decoder IOCTL_SET_VE_FREQ
Attempt to set the cedar clock rate based on the actual PLL4
clock rate, not some hard-coded rate.  Computes an integer
divisor of pll4clk_rate between 1 and 8 (inclusive) such that
the resulting VE clock rate is >= the requested rate but
within the the min/max speed range of 100MHz -- 320MHz.
sunxi:cedar Make all video data memory DMA coherent
Set pgprot_dmacoherent on all CedarX DMA memory.  Video buffers
in __videobuf_mmap_mapper in videobuf-dma-contig.c were allocated
with dma_alloc_coherent prior to the addition of the sunxi_ve_mem_reserve
kernel argument.