Initial work on new module system

NOTE: This code is difficult to run, since the namespaces have cyclic
dependencies now. This should be refactored before pushing.
Organize namespaces for new modules, support inputs
Additional progress on new modules, now supporting all of the tests for old modules
Start porting tests to modulize
Port all tests over to new module system
Switch to use ->verilog in sw_led test
Merge branch 'master' into new-modules
Remove a bunch of unused code in verilog codegen
Remove trailing whitespace
Document the verilog converter
Refactoring verilog code generator
Fix not= to properly make AST
Initial work on arrays for simulation
Add zero? pos? and neg?
Preliminary stab at verilog codegen for modules
Add support for memories in simulation and verilog synthesis
Remove old modules/connect from everywhere and remove unused verilog templates
Fix bug in input specification
Now that new-modules is merged, no need to keep using it