ARC: [SMP] STAR 9000597649 workaround

When doing TLB flush, simulator (nSIM)
trigger flush of internal cache (designed for optimization).

Signed-off-by: Noam Camus <noamc@ezchip.com>
Signed-off-by: Anton Kolesov <akolesov@synopsys.com>
NET: Add network driver

This patch adds an driver for the debug LAN device used in EZchip NPS boards.

Signed-off-by: Noam Camus <noamc@ezchip.com>
ARC: [plat-eznps] Add eznps platform

This platform include boards:
	Hardware Emulator (HE) version 0,1...
	Simulator based upon nSIM.

Signed-off-by: Noam Camus <noamc@ezchip.com>
ARC: [plat-eznps] Add eznps default board configurations

Signed-off-by: Noam Camus <noamc@ezchip.com>
ARC: [plat-eznps] Add eznps DTS file

Signed-off-by: Noam Camus <noamc@ezchip.com>
ARC: [plat-eznps] Add device for Data Plane Linux

Add new device /dev/dpl.
This device enable access to cmem in other cores.

It is usefull for debugging when gdbserver is attached to process
which runs in a different CPU than gdbserver.

Signed-off-by: Noam Camus <noamc@ezchip.com>
Signed-off-by: Tal Zilcer <talz@ezchip.com>
ARC: [SMP] TLB flush

This is for cases we need to flush tlb's in several CPU's since a memory
structure may be held by several threads in the same time in different
CPU's.

Signed-off-by: Noam Camus <noamc@ezchip.com>
ARC: [SMP] ASID handle

Each CPU got its own TLB and therefore it's own software cache.
Each mmu context may reside at the same time in several CPU's
thanks to posix threads sharing the context.
Therefore may have different ASID.

Signed-off-by: Noam Camus <noamc@ezchip.com>
ARC: Add initrd from external file.

We now can easly get rootfs from external file.
It may be cpio, ext2, cramfs...

This makes vmlinux usable not only for internal cpio.

Signed-off-by: Noam Camus <noamc@ezchip.com>
ARC: Handle un-aligned user space access in BE.

Adding endian awarness to un-aligned access exception handling.

Signed-off-by: Noam Camus <noamc@ezchip.com>
ARC: Change IRQ init order.

this is workaround
Need to reverse implementaion inside platform

Signed-off-by: Noam Camus <noamc@ezchip.com>
ARC: add CPUSET/NOHZ syscall hooks

CPUSET/NOHZ requires hook for each entry and exit from kernel
of dyntick enabled task.

Signed-off-by: Noam Camus <noamc@ezchip.com>
ARC: add CPUSET/NOHZ fault/trap handling hooks

CPUSET/NOHZ requires hooks for entry and exit from/to kernel.
This patch adds the needed ARC hooks for traps and faults.

Signed-off-by: Noam Camus <noamc@ezchip.com>
ARC: [plat-eznps] add support for NO_HZ_FULL

Select configuration needed as NO_HZ_FULL deps.

Signed-off-by: Noam Camus <noamc@ezchip.com>
time: remove 64BIT config dep for NO_HZ_FULL

Although ARC is 32BIT I still wan't to use NO_HZ_FULL.

Signed-off-by: Noam Camus <noamc@ezchip.com>
vmstat: remove vmstat workqueue.

With NO_HZ_FULL the task of vmstattimer is annoying.

Signed-off-by: Noam Camus <noamc@ezchip.com>
ARC: add use of schedule_user

only when CONFIG_CONTEXT_TRACKING

Signed-off-by: Noam Camus <noamc@ezchip.com>
ARC: gdbserver breakage in Big-Endian configuration #1

Exception handling keeps additional state (whether exception was Trap
and if it was due to a breakpoint) in pt_regs->event, a bitfield member

        unsigned long orig_r8:16, event:16;

A bitfield esentially has an "offset" and a "length". What I wasn't
aware of was that, bitfields in a union loose the "offset" attribute
and all of them are laid out at offset 0.

This obviously means that both @event and @orig_r8 will be incorrectly
referenced to at same "0" offset by "C" generated code which is
certainly wrong, not because both members are accessed, but because asm
code updates it at different address.

In Little Endian config, @event is at offset 0 and @orig_r8 (not
actively used at all) clashing with it is OK. However in Big Endian
config,

	ST 0xNNNN_EEEE, [addr]

writes 0xEEEE to @event (offset 2 in memory) while "C" code references
it from 0.

Needless to say, this causes ptrace machinery to not detect the breakpoint
scenario (and incorrect stop_pc returned to gdbserver).

------>8---------------
Thi issue is already fixed in mainline 3.11 kernel as part of commit:
502a0c775c7f0a "ARC: pt_regs update #5"

However that patch has lot more changes than I would like backporting,
hence this seperate change.
------>8---------------

Reported-by: Noam Camus <noamc@ezchip.com>
Cc: <stable@vger.kernel.org> # [3.9 and 3.10 only]
Tested-by: Anton Kolesov <akolesov@synopsys.com>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
ARC: gdbserver breakage in Big-Endian configuration #2

This is related to how how different asm instructions write to a
bitfield member.

In BE config, @orig_r8 is at offset 0 while @event is at offset 2.

"ST 0xNNNN_EEEE, [addr]" correctly writes 0xEEEE to @event, however
a half word write, "STW 0xEEEE, [addr]" does not in Big Endian while
works perfectly file for LE config (since @event is at offset 0).

------>8---------------
Thi issue is already fixed in mainline 3.11 kernel as part of commit:
502a0c775c7f0a "ARC: pt_regs update #5"

However that patch has lot more changes than I would like backporting,
hence this seperate change.
------>8---------------

Reported-by: Noam Camus <noamc@ezchip.com>
Cc: <stable@vger.kernel.org> # [3.9 and 3.10 only]
Tested-by: Anton Kolesov <akolesov@synopsys.com>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>