risugen: add --not-pattern flag for convenience

The --pattern flag is useful for including whole classes of instructions.
You could also do specific instruction with it. However if you want a
whole class of instructions without a specific few instructions you'd
need to come up with a more complex regex.

With this you can for example to:

  risugen --pattern ".* A64" --not-pattern "ROR.*" aarch64.risu test3.bin
aarch64.risu: add C3.6.25 Floating-point data-processing (1 source)

this adds C3.6.25, including

FMOV (register), FABS (scalar), FNEG (scalar), FCVT,
FSQRT (scalar), FRINT (scalar)

Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>
risugen: change floating point randomization for aarch64

generate "interesting" values for aarch64 as well,
in the same way as we do for ARM.

Also disable use of LD1 to load 4 regs at a time, for now,
and replace with LDP Qn, which loads only 2 regs at a time.
As LD1 is implemented and stable, we can switch back to use it.

Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>
aarch64.risu: add C3.6.26 Floating-point data-processing (2 source)

this adds C3.6.26, including

FMUL (scalar), FNMUL, FDIV (scalar), FADD (scalar), FSUB (scalar),
FMAX (scalar), FMIN (scalar), FMAXNM (scalar), FMINNM (scalar)

Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>
aarch64.risu: add C3.6.27 Floating-point data-processing (3 source)

this adds C3.6.27, including FMADD, FMSUB, FNMADD, FNMSUB.

Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>
aarch64.risu: add C3.6.28 Floating-point immediate

this adds C3.6.28, including FMOV (scalar, immediate).

Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>
aarch64.risu: add C3.6.29 Floating-point_fixed-point conversions

this adds C3.6.29, including
SCVTF (scalar, fixed-point), UCVTF (scalar, fixed-point),
FCVTZS (scalar, fixed-point), FCVTZU (scalar, fixed-point).

Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>
aarch64.risu: add C3.6.30 Floating-point_integer conversions

this adds C3.6.30, including

FCVTNS (scalar), FCVTNU (scalar),
SCVTF (scalar, integer), UCVTF (scalar, integer),
FCVTAS (scalar), FCVTAU (scalar),
FMOV (general), FCVTPS (scalar), FCVTPU (scalar),
FCVTMS (scalar), FCVTMU (scalar),
FCVTZS (scalar, integer), FCVTZU (scalar, integer)

Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>
aarch64.risu: add C3.6.6 AdvSIMD modified immediate

this adds C3.6.6, including

MOVI, ORR (vector, immediate), FMOV (vector, immediate),
MVNI, BIC (vector, immediate)

Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>
aarch64.risu: fix logical immediate constraints

the constraints on logical immediate are too tight,
disallowing valid sf + N field combinations.
At the same time, the ReservedValue test cases were also
incorrect in the same way.

Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>
aarch64.risu: add C3.6.22 Floating-point compare

this adds C3.6.22 including

FCMP (single precision, single precision zero)
FCMPE (single precision, single precision zero)

FCMP (double precision, double precision zero)
FCMPE (double precision, double precision zero)

Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>
aarch64.risu: add C3.6.23 Floating-point Conditional Compare

this adds C3.6.23, including

FCCMP (single precision, double precision)
FCCMPE (single precision, double precision)

Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>
aarch64.risu: add C3.6.24 Floating-point conditional select

this adds C3.6.24, including

FCSEL (single precision), (double precision)

Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>
risu.c: add basic usage() text
aarch64.risu: allow encoding of hw field for movi

The hw field indicates a shift
emacs tag for editing mode
risu: a bit more verbosity when running

Before this is could seem a little quite when running as you had no
indication stuff was happening (or how fast). I only dump on the master
side as I want to minimise the amount of qemu logs to sift through.
risu: enable static builds
Add "dump" target to Makefile

This will dump any risu.bin files to the risu.asm files which are so
useful for working through stuff. Of course you can run an individual
make target by running:

make simd_copy.risu.asm