Use GCC's __attribute__((const)) to reduce code size

__attribute__((const)) is mainly intended for the compiler to optimize
away repeated calls to a function that the compiler knows will return
the same value repeatedly.

By adding __attribute__((const)), the compiler can choose to call the
function just once and cache the return value.  Therefore, this yields
code size reduction.

Here are the reference results by arm-eabi-size for crespo device:

[before]
   text    data     bss     dec     hex filename
 267715   10132   45948  323795   4f0d3

[after]
   text    data     bss     dec     hex filename
 267387   10132   45948  323467   4ef8b

Change-Id: I1d80465c0f88158449702d4dc6398a130eb77195
getopt(): fix missing carriage return on bad parameters

This affect all command line tools which show the usage on stdout
after an invalid parameter error (printed on stderr)

Change-Id: I8e2cb3fda241ab989dc42055f15082f8b3ba1397
Signed-off-by: Tanguy Pruvot <tanguy.pruvot@gmail.com>
headers: Unbreak some ARM syscalls

Restore the outside-kernel exclusion for some syscalls that was
removed by change I959b64280e184655ef8c713aa79f9e23cb1f7df4,
since these syscalls are used elsewhere.

Change-Id: I5b5bf3d78edd137e820d25281a375966b6c009ec
libc: krait: Restore prior version of strcmp.

Change-Id: I8ddcdb4d3a905dd746985435dcdb525ab5a1c947
libc/arm: add cortex-a8 cpu variant

Change-Id: I30e8dd6d4b2e7889aea8f5ed21182a5941bfb489
Bionic/libm: fast neon pow() for small x,y.

Add a fast neon version of pow() suitable for relatively small
positive x and y (between 0 and 4).  Run the standard
implementation in all other cases.  Gives approximately 60%
performance improvement to AnTuTu FPU scores

Change-Id: I97e0712daeb2740764b26a44be0caaa39c481453
Bionic/libm: Prefer branches and VFP ABI.

For internal functions set gcc attribute "aapcs-vfp" for ARM
and use -fno-if-conversion to prefer branches over predicated
instructions (improves performance on architectures with good
branch prediction).

Change-Id: I8424e0e82a19d35e7e3b6e3e122dcdecdd5426fd
Bionic/libm: Pow optimizations and bug fixes.

Use VFP calling convention for pow_neon handoff function by default.
Fix register usage collision between two different polynomial
coefficients in pow_neon.  Remove conditional execution in pow_neon
and replace with branching.

Change-Id: I76095f4a006e2fb01a53943b66fd69bfa1fd3033
linker: restore prelink support

Prelink support is required to load old vendor binary blobs
on many devices properly

This commit partially reverts 4688279db5dcc4004941e7f133c4a1c3617d842c

Change-Id: Iee5325e048daee78e8dcaa47c87454b908c89b4e
libc: Add Scorpion-optimized memcpy and memset

 * Optimized routines from Qualcomm for msm8660 class SoCs
 * Enable with TARGET_CPU_VARIANT := scorpion

Change-Id: I01d0f22efba5a418ddd20fca0d0c570d855e0f6f
libc: Use the fast strlen on Scorpion too

Change-Id: I9ba50a469de27269adc008c2a96767830ad6b70b
libc: arch-arm: strlen: Illegal ARM entries fixed

Spacing between brackets is a illegal ARM entry

PS1 - Inital patch
PS2 - update description and rebase

Signed-off-by: Paul Beeler <sparksco@gmail.com>

Change-Id: I52d7e95a8afb8b26f55fe0bc01853a15a95e90c2
libc: Update to latest cortexa15 memcpy code.

This uses the new code original submitted as memcpy.a15.S as
the base. However, the old code handled unaligned src/dst better
so that was spliced in. I optimized the original unaligned code by
removing a few unnecessary instructions. I optimized the a15 code by
rewriting the pre and post code. I also modified the main loop to add
a pld so that larger copies would not stall waiting for memory.

Test cases for the new memcpy:

- Copy all sized values from 0 to 1024 bytes, using whatever alignment
  is returned by malloc.
For each alignment case described below, the test copied from 0 to 128
bytes.
- Src and dst pointers are both aligned to the same value, starting
  at one going through every power of two up to and including 128.
- Src aligned to double word boundary, dst aligned to word boundary.
- Src aligned to word boundary, dst aligned to double word boundary.
- Src aligned to 16 bit boundary, dst aligned to word boundary.
- Src aligned to word boundary, dst aligned to 16 byte boundary.
- Src aligned to word boundary, dst aligned to 1 byte from a word
  boundary.
- Src aligned to word boundary, dst aligned to 2 bytes from a word
  boundary.
- Src aligned to word boundary, dst aligned to 3 bytes from a word
  boundary.
- Src aligned to 1 byte from a word boundary, dst aligned to a word
  boundary.
- Src aligned to 2 bytes from a word boundary, dst aligned to a word
  boundary.
- Src aligned to 3 bytes from a word boundary, dst aligned to a word
  boundary.

Cases to verify the unaligned source code properly aligns to a 16 bit
boundary.
- Src aligned to 1 byte from a 128 bit boundary, dst aligned to
  4 + 128 bit boundary.
- Src aligned to 1 byte from a 128 bit boundary, dst aligned to
  8 + 128 bit boundary.
- Src aligned to 1 byte from a 128 bit boundary, dst aligned to
  12 + 128 bit boundary.
- Src aligned to 1 byte from a 128 bit boundary, dst aligned to
  16 + 128 bit boundary.

In all cases, a two byte fencepost was placed at the end of the
destination to verify that only the requested number of bytes were copied.

Bug: 8005082

Merge from internal master.

(cherry-picked from commit 21ede92d794969f22cacbdb9f557818f1c5712b5)

Change-Id: Ief70c9e6dc8c6473ae245b6570b2c266fed9618c

Add missing branch in memcpy.S dst aligned case.

Merge from internal master.

(cherry-picked from commit 6ffaa931c362602a2b606a610c92326a425a876e)

Change-Id: Ifdcf01fd122866cf0d4c5b5f7a997803561d7889

Rewrite memset for cortexa15 to use strd.

Merge from internal master.

(cherry-picked from commit 7ffad9c120054eedebd5f56f8bed01144e93eafa)

Change-Id: Ia67f2a545399f4fa37b63d5634a3565e4f5482f9
Fix assembler errors in generic arm strlen.c.

Tested using a static version of the strlen libc_test program
on a nexus7 that uses the generic code.

Merge from internal master.

(cherry-picked from d8d10a8994472e40d19301b7087806630877b4d5)

Change-Id: I88f7dc01dc5b5c3ac2d5580d92153bc1bc36c564
libc: add tegra2 TARGET_CPU_VARIANT

Tegra2 is a Dual Cortex A9 without FP neon SIMD

based on 'generic' arm (memcpy, memset)
on cortex-a15 and a8 (strcmp)
and armv7-a from cm10.1 (memchr and strlen)

rebased and now for cm-10.2 only

Change-Id: I1e7207e2d1ba02012fb5306f46b688903d31386c
Signed-off-by: Tanguy Pruvot <tanguy.pruvot@gmail.com>
don't hardcode register r0/v1 when reading the TLS

this leads to much improved code when calling __get_tls()

Change-Id: I21d870fb33c33a921ca55c4e100772e0f7a8d1e4
tegra2: add missing strcpy and strcat

These applets are no more common since recent optimisations

strcpy from cortex-a9
strcat : keep standard one

Change-Id: Icfedf17aa4f9fa30e7f63b19bd6d4ac533e5e0e9
Detect userspace memory leak for JB_MR2

When process is consuming memory beyond the limit specified by
property, it will print all the allocations of the same process.
To enable this feature, do following steps:
1. libc.debug.malloc 40
2. libc.debug.malloc.program <PROCESS_NAME>
3. libc.debug.malloc.maxprocsize <VALUE_IN_BYTES>
4. libc.malloc.minalloclim <VALUE_IN_BYTES>

Change-Id: I03a4de9643ec954802b26443ce5685975ea30f89
Signed-off-by: Maunik Shah <mshah@codeaurora.org>
Bump the number of TLS slots to 128.

Bug: 9997352
Change-Id: I7bde7228d803e9d4bb83309c5891d54a07e3b025
add cortex-a5 cpu variant

Change-Id: I3f72fa4524c09d3ea9abcc3a4a693f563e58ed53