cache: remove drainManager because it's not used

the cache drainManager is set but never cleared, this is because
the cache itself does not need to be drained and thus never
triggers a signalDrainDone(). because the drainManager variable
is not used properly and does not appear to be necessary it has
been removed with this patch.
mem: Separate out the different cases for DRAM bus busy time

This patch changes how the data bus busy time is calculated such that
it is delayed to the actual scheduling time of the request as opposed
to being done as soon as possible.

This patch changes a bunch of statistics, and the stats update is
bundled together with the introruction of tFAW/tTAW and the named DRAM
configurations like DDR3 and LPDDR2.
mem: Add tTAW and tFAW to the SimpleDRAM model

This patch adds two additional scheduling constraints to the DRAM
controller model, to constrain the activation rate. The two metrics
are determine the size of the activation window in terms of the number
of activates and the minimum time required for that number of
activates. This maps to current DDRx, LPDDRx and WIOx standards that
have either tFAW (4 activate window) or tTAW (2 activate window)
scheduling constraints.
mem: Add DDR3 and LPDDR2 DRAM controller configurations

This patch moves the default DRAM parameters from the SimpleDRAM class
to two different subclasses, one for DDR3 and one for LPDDR2. More can
be added as we go forward.

The regressions that previously used the SimpleDRAM are now using
SimpleDDR3 as this is the most similar configuration.
stats: Update stats for regressions using SimpleDDR3

This patch updates the regression stats to reflect that they are using
the SimpleDDR3 controller by default.
mem: Add comments for the DRAM address decoding

This patch adds more verbose comments to explain the two different
address mapping schemes of the DRAM controller.
ruby: correct computation of number of bits required for address
The number of bits required for an address was set to floorLog2(memory size).
This is correct under the assumption that the memory size is a power of 2,
which is not always true. Hence, floorLog2 is being replaced with ceilLog2.
sim: remove unused struct priority_compare
cpu: Remove incorrect branch predictor drain checks

The branch predictor unit incorrectly checked that the prediction
history was empty when the system is drained. This is an incorrect
assumption since the predictor isn't affected by a drain.
cpu: Set memReq[tid] to NULL in finishTranslation after squashes

DefaultFetch::finishTranslation() sometimes deleted the incomming
memory request without clearing the associated memReq pointer. This
caused an assertion in DefaultFetch::drainSanityCheck to fail. This
changeset sets memReq[tid] to NULL if the request that is discarded
matches the request the fetch stage is currently waiting on.
config: Don't call sys.exit in interactive mode in run()

The run() method in Simulation.py used to call sys.exit() when the
simulator exits. This is undesirable when user has requested the
simulator to be run in interactive mode since it causes the simulator
to exit rather than entering the interactive Python environment.
base: Fix broken IPython argument handling

Prior to this changeset, we used to clear sys.argv before entering the
IPython shell. This caused some versions of IPython to crash because
they assume argv[0] to exist. The correct way of overriding the
arguments passed to IPython is to set the argv keyword argument when
initializing the shell.
base: Add support for newer versions of IPython

IPython is used for the interactive gem5 shell if it exists. IPython
made API changes in version 0.11. This patch adds support for IPython
version 0.11 and above.