target-arm: aarch64: add support for 'test and branch' imm

this patch adds emulation for the test and branch insns,
TBZ and TBNZ.

Signed-off-by: Alexander Graf <agraf@suse.de>

[claudio: adapted for new decoder,
          always compare with 0, remove a TCG temporary]

Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>

From Alexander Graf <agraf@suse.de> aarch64 series 40/60
target-arm: aarch64: add support for compare and branch imm

this patch adds emulation for the compare and branch insns,
CBZ and CBNZ.

Signed-off-by: Alexander Graf <agraf@suse.de>

[claudio: adapted to new decoder,
          compare with immediate 0, use read_cpu_reg to get
          the 0 extension on (!sf)]

Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>

From Alexander Graf <agraf@suse.de> aarch64 series 33/60
target-arm: aarch64: add support for EXTR

This patch adds emulation support for the EXTR instruction.

Signed-off-by: Alexander Graf <agraf@suse.de>

[claudio: adapted for new decoder, removed a few temporaries,
          fixed the 32bit bug, added checks for more
          unallocated cases]

Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>

From Alexander Graf <agraf@suse.de> aarch64 series 30/60
AArch64: Add stubs for a64 specific helpers

We will need helpers that only make sense with AArch64. Add
helper-a64.{c,h} files as stubs that we can fill with these
helpers in the following patches.

Signed-off-by: Alexander Graf <agraf@suse.de>

From Alexander Graf <agraf@suse.de> aarch64 series 13/60
target-arm: aarch64: add support for 2-src data processing and DIV

this patch adds support for decoding 2-src data processing insns,
and the first users, UDIV and SDIV.

Signed-off-by: Alexander Graf <agraf@suse.de>

[claudio: adapted to new decoder adding the 2-src decoding level,
          always zero-extend result in 32bit mode]

Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>

From Alexander Graf <agraf@suse.de> aarch64 series 44/60
target-arm: aarch64: add support for 2-src shift reg insns

this adds 2-src variable shift register instructions
C5.6.115 LSLV, C5.6.118 LSRV, C5.6.17 ASRV, C5.6.154 RORV

Signed-off-by: Alexander Graf <agraf@suse.de>

[claudio: adapted to new decoder]

Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>

From Alexander Graf <agraf@suse.de> aarch64 series 45/60
target-arm: aarch64: add support for 1-src data processing and CLZ

this patch adds support for decoding 1-src data processing insns,
and the first user, C5.6.40 CLZ(count leading zeroes).

Signed-off-by: Alexander Graf <agraf@suse.de>

[claudio: adapted to new decoder, simpler path for 64bit form,
          reuse 32bit helper for 32bit form]

Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>

From Alexander Graf <agraf@suse.de> aarch64 series 47/60
target-arm: aarch64: add support for 1-src RBIT insn

this adds support for the C5.6.147 RBIT instruction.

Signed-off-by: Alexander Graf <agraf@suse.de>

[claudio: adapted to new decoder, use bswap64,
          make RBIT part standalone from the rest of the patch,
          will handle REV in a separate patch]

Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>

From Alexander Graf <agraf@suse.de> aarch64 series 46/60
target-arm: aarch64: add support for 1-src REV insns

this adds support for C5.6.149 REV, C5.6.151 REV32, C5.6.150 REV16.

Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>

From Alexander Graf <agraf@suse.de> aarch64 series 46/60
target-arm: aarch64: add support for bitfield insns

this patch supports C3.4.2 Bitfield instructions
SBFM, BFM, UBFM.

Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org>

From Alexander Graf <agraf@suse.de> aarch64 series 31/60
default-configs: Add config for aarch64-linux-user

Add a config for aarch64-linux-user, thereby enabling it as
a valid target.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
translate-a64.c: add new-line to log message
translate-a64.c: dump subject pc on unalloc enc

This turns out to be fairly handy when you are trying to figure out how
far into the binary you have got.
linux-user/signal.c: dump pc when aborting

It doesn't hurt and it certainly helps when bringing up new instructions
when it breaks.
.travis.yml: add aarch64-linux-user target
target-arm: aarch64: add support for add and addi

This patch combines two of the original series for generic add
implementation support.

from Alexander Graf <agraf@suse.de> aarch64 series 15/60 (- extended)
from Alexander Graf <agraf@suse.de> aarch64 series 27/60

---

v2 -> v3:

      - use extract32/sextract32 instead of get_bits and get_sbits
      - open code get_reg()

v3 -> v4 (ajb):
      - removed the flag handling helpers, stubbed out TCG equivalent
      - streamlined the generation to avoid duplication

v4 -> v5 (ajb):
      - used Claudio's common add_with_carry for flag ops
      - common as much as possible between addi/add
      - removed extraneous diagrams
      - documented the add (extended register) stub

v5 -> v6 (ajb):
      - drop add_with_carry for now

v6 -> v7 (ajb):
      - fixed dodgy tcg generation.
target-arm: aarch64: add support for stp (store pair)

This patch support basic GPR based store-pair instructions and includes
the generic do_gpr_st() function for store routines.

from Alexander Graf <agraf@suse.de> aarch64 series 11/60

---

v2 -> v3:

      - use extract32/sextract32 instead of get_bits and get_sbits
      - drop get_reg()
      - open code get_reg()

v3 -> v4
      - split from bigger patch (non vector)
      - better naming?
target-arm: aarch64: add support for movi

This patch adds emulation for the movi instruction. This includes the
various movn, movz and movk forms.

Signed-off-by: Alexander Graf <agraf@suse.de>

---

    v2 -> v3:

      - use extract32/sextract32 instead of get_bits and get_sbits
      - open code get_reg()

    v3 -> v4 (ajb):

       - applied RH's constant folding comment
       - move cpu_reg allocation to top
target-arm: aarch64: add support for ld/st unsigned imm

This adds support for the basic non-vector form of ld/st with and
unsigned immediate offset. This was split from the original patch from
Alexander due to re-factoring due to the changes in the decoder.

from Alexander Graf <agraf@suse.de> aarch64 series 41/60
target-arm: aarch64: add support for ld lit

Adds support for Load Register (literal).

from Alexander Graf <agraf@suse.de> aarch64 series 40/60