mtd: nand: mxs: reset BCH earlier, too, to avoid NAND startup problems

It could happen (1 out of 100 times) that NAND did not start up
correctly after warm rebooting, so barebox could not find its
environment or DMA timed out due to a stalled BCH. When resetting BCH
together with GPMI, the issue could not be observed anymore. We probably
need the consistent state already before sending commands to NAND.

Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
ARM i.MX6: fix ethernet PLL rate

The ethernet PLL has a fixed frequency of 500MHz. What is adjustable
are additional dividers which we better describe separately.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
ARM i.MX6: rename PLLs according to datasheet

In recent reference manuals the plls were renumbered. PLL8 now is
PLL6 and vice versa. Change the code according to the reference
manual to avoid confusion.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
clk: Add clk table based divider support

For easy support of table based dividers.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
ARM i.MX6 pllv3: Do not use delay functions

We may be called very early, before the timer is available,
so don't use it here.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
ARM i.MX6 clk: remove gate_mask from pllv3

Not needed as we will handle the additional gate bits as gate.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
ARM i.MX: Add driver to get sdram base and size

The code initializing the SDRAM controller is not at the same
place where SDRAM is registered with barebox. To reduce the
risk of registering wrong SDRAM sizes this patch adds a
driver for the ESDCTL which reads back the configured SDRAM
size and registers the memory found with barebox.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
ARM i.MX: register esdctl controller device

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
ARM i.MX boards: use esdctl code to detect sdram size

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
ARM i.MX bbu: Allow to overwrite app_dest

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
ARM i.MX bbu: Allow to have no DCD

Some boards do not have a DCD table since they initialize everything
in code, so allow to skip it and leave the corresponding pointers
empty.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
ARM i.MX5: move pll setup defines to header file

The pll setup function is exported, so it makes sense to export
the convenience wrappers for specific frequencies aswell.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
ARM i.MX: add esdctl-v4 support

This adds support for initializing DDR3 RAMs on the i.MX53 type
SDRAM controller. The code automatically detects size/layout of
the connected RAM, detects the bus width and which chipselects are
populated.
While I believe this code is not 100% generic, it is far too
sophisticated to stay in a single board directory. I'm sure
other boards could make use of this aswell.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
ARM i.MX esdctl: Use defines from exisiting header file

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
ARM i.MX: Add Garz+Fricke Vincell Board support

This adds support for the Garz+Fricke Vincell board. This has
a i.MX53 Processor with 512MB of DDR3 RAM.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
ARM i.MX bbu: Add i.MX6 MMC handler

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
ARM i.MX bbu internal: Add spi/i2c support

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
ARM i.MX6: save boot location

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
ata: Add i.MX PATA driver support

Straight forward driver, we only have to configure some additional
bits and then use the generic ide support.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
ARM i.MX: Add i.MX51 PATA device support

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>