Remove comma in Verilog that makes ModelSim angry.
Parameterize WS2812 signal durations.
Factor out the RAM block from the WS2812 protocol module.
Refactor pixel RAM to implement only what's necessary (no read of port A, no write of port B).
Ignored files cluttering up my repo.
Revise ws2812 module to use module parameter syntax.
Rename some ws2812 signals to make them shorter but clearer.
Extract signal led_pixel_count_advance.
Extract led_pixel_count_init value and use it at reset to address first-pass strip readout bug, where 512 pixels are transmitted before settling into the proper LED strip length cadence.
Renamed led_pixel_last to be more descriptive "led_pixel_count_last".
Fix bug where last pixel in strip was not being read out.
Refactor signals of led_symbol_count*, and rename an ambiguous signal.
Rewrite of ws2812 module to address pipelining issues. Implementation is now not particularly pipelined, but a lot easier to follow...
Quartus II .qsf project file automatically updated by version 13.1, with a bunch of stuff randomly moved around.
Super-basic ws2812 testbench for observing behavior in the simulator.
Add 24-bit color support, parameter for selection.
Remove dead comments and code.
Nail down unused strip outputs.
Clean up sensitivity list warnings.