Add a test case for PR14750.

This was fixed by r174402.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174405 91177308-0d34-0410-b5e6-96231b3b80d8
Move MRI liveouts to ARM return instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174406 91177308-0d34-0410-b5e6-96231b3b80d8
Move MRI liveouts to Hexagon return instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174407 91177308-0d34-0410-b5e6-96231b3b80d8
Move MRI liveouts to MBlaze return instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174408 91177308-0d34-0410-b5e6-96231b3b80d8
Move MRI liveouts to PowerPC return instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174409 91177308-0d34-0410-b5e6-96231b3b80d8
Move MRI liveouts to Mips return instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174410 91177308-0d34-0410-b5e6-96231b3b80d8
Move MRI liveouts to MSP430 return instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174411 91177308-0d34-0410-b5e6-96231b3b80d8
Hexagon: Use multiclass for absolute addressing mode stores.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174412 91177308-0d34-0410-b5e6-96231b3b80d8
Move MRI liveouts to Sparc return instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174413 91177308-0d34-0410-b5e6-96231b3b80d8
Move MRI liveouts to XCore return instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174414 91177308-0d34-0410-b5e6-96231b3b80d8
Move MRI liveouts to AArch64 return instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174415 91177308-0d34-0410-b5e6-96231b3b80d8
Remove special-casing of return blocks for liveness.

Now that return value registers are return instruction uses, there is no
need for special treatment of return blocks.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174416 91177308-0d34-0410-b5e6-96231b3b80d8
Remove liveout lists from MachineRegisterInfo.

All targets are now adding return value registers as implicit uses on
return instructions, and there is no longer a need for the live out
lists.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174417 91177308-0d34-0410-b5e6-96231b3b80d8
[SjLj Prepare] When demoting an invoke instructions to the stack, if the normal
edge is critical, then split it so we can insert the store.
rdar://13126179

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174418 91177308-0d34-0410-b5e6-96231b3b80d8
Hexagon: Add testcase for post-increment store instructions.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174419 91177308-0d34-0410-b5e6-96231b3b80d8
Loop Vectorizer: Refactor code to compute vectorized memory instruction cost

Introduce a helper class that computes the cost of memory access instructions.
No functionality change intended.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174422 91177308-0d34-0410-b5e6-96231b3b80d8