[tilegx] Add float point register class.

  For tilegx, float point reuse integer register class.
After this change, we need to specify the operand type
explictly in .td file, because one register class may
infer to two types.

  CPURegs   => both i64 and f64
  CPU32Regs => both i32 and f32

  [(set CPURegs:$rd,
        ~~~~~~~
             |
             V
             (i64 or f64?)
         (add CPURegs:$rs, immSExt8:$imm8))],

  [(set (i64 CPURegs:$rd),
         ~~~~~~~~~~~~~~~
             |
             V
             (specify "i64" explictly)
         (add CPURegs:$rs, immSExt8:$imm8))],
[tilegx] Add a new .td file to describe float point instructions.

  ChangeLog:
    lib/Target/Tile/TileInstrFP.td: New file.
TILE-Gx has partial hardware float point support.
  1. No dedicated float regs, reuse integer regs.
  2. Only support parts of float operations, mul/add etc,
     no support of type conversions, for example, fp->dp etc.

So our implementation for float support is:

  1. We pretend to have complete hardware float support.
     reuse integer regs as float regs.

  2. Lower invalid float op into lib call in ISelLowering pass.

  3. Split valid float op into corresponding inst sequences in
     ISelDAGToDAG pass. Because even for those valid ops, they
     can not be finished by a single instructions, we need a
     instruction combination to finish the work.
[tilegx] Support double precision float multiply.

  We need to use a series of instructions to finish double float
multiply. The instruction sequences is copied from TILE-Gx gcc.

  We can't do the instuction expanding in ExpandPseudo pass, because
the register def/use is complex in double float compared with single
float multiply, thus the expand is in ISelDAGToDAG pass which runs
before regalloc.
[tilegx] Reformat modified files with clang-format. No function changes.
[tilegx] Add hardfloat compare support.

  All float compare operations are assigned with a pseudo instruction.
For exmpale, "fp < fp" are assigned FSINGLE_CMP_LT, which will be
expanded into:

  fsingle_add1
  bfextu

  The expanding is occurred before instruction scheduling, so the new
instructions could be scheduled.
[tilegx] reimplement float multiply according to gcc .md file.
[tilegx] Added FADD/FSUB/FDIV support.

  FADD/FSUB patterns are borrowed from gcc .md.
  FDIV expanded into libcall.
[tilegx] Fix float calling conv bug. Missed f32 arg passing rule.

  previously, softfloat always used, so float type are converted to integer
type, thus never trigger the f32 arg passing bug.
[tilegx] Remove obsolete target private opcode.
[tilegx] Add i/u64 => float/double conversion

  No hardware support for these conversions. Use softfloat approach.
[tilegx] Support all other float type conversions.

  i32 => f32, i32 => f64, u32 => f32, u32 => f64,
  f32 => f64, f64 => f32
[tilegx] Support unorder comparison.
[tilegx] Fix compile warning on gcc 4.7.
[tilegx] Handle float point intrinsics in hard-float mode.

  No hard-float support for these intrinsics, need to expand them into
equivalent instruction sequences or lib call.
[tilegx] Support -soft-float.

  We use hard-float by default, but if -soft-float specified, turn to
soft float instead.
[tilegx] Support new hard-float instructions in MC Layer.