BUG FIX wishbone utils didn't add non wishbone wires
DESIGN CHANGE: Moved the o_mem_adr increment

Before the o_mem_adr incremented when new data was read from the host.
The problem with this is that there are two dependencies for this. The
wishbone bus and the host interface. Moving this into the 'acknowledge
condition' reduces the dependencies on the host interface.
BUG FIX: Small SDRAM fixes and some support files

The major bug in the SDRAM core was that the wb_sdram only read in even
values from the wishbone interconnect. This was a residual effect from
migrating the memory count from the byte level access to the 32-bit word
interface.
ASTHETIC CODE CHANGES: Formatting of verilog
BUG FIX: wb_mem_2_ppfifo memory empty status fix

Empty flag was not correctly reporting empty status
ASTHETIC CHANGE: logic analyzer formatting
MUSIC!!!

Lots of bug fixes all over the I2S core but the audio works clearly
ADD: Lots of debug configuration files for I2S

All these added I2S configuration files are for debugging the audio core
with the logic analyzer