Generalized implementation of M6810, no longer dependent on Xilinx RAMB16_S9.
Renamed 7447.vhd to 7442.vhd, since it actually implements the DM7442.
Updated Xilinx project (.XISE) file.
Additional changes from renaming 7447.vhd -> 7442.vhd.
Factor out common sound module, for use by board/silicon-specific top module.
Reworked schematic to allow easier pin-swapping.
New board layout that is more representational of how the board plugs into the FPGA board.
Hirose FX2 connector flipped to front side of board.
Added BA pull-up to ensure address/data bus buffer OE#s are under control when MPU is not driving.
Complete re-ordering of signals to FPGA board FX2 connector.