hdl/*: (1/3) massive dsp changes

* Changed to a Time-division multiplexing approach.
	We are using a 2-multilplexed stream scheme for
	high frequencies (ADC rate) and a 4-multiplexed
	stream scheme for all the other lower rates.

* Oversampling rate of 2 relative to ADC rate.
	Now, a 2xADC rate clock is used for all the
	DSP chain. It allows for a reduced number of
	resources usage	at higher rates.

* Fix delta-sigma pre-divider FIFO buffers

* Add 25-bit multipliers for Kx, Ky and Ksum (position
measurement constants)

* Lower order of BPF at the beggining of the chain, in order
to reduce the number of FPGA resources used (mainly DSP48E1).
Also, we are using an oversample rate of 2, so, rougly, 2 times
less resources are used.

TODO:

* 4-channel DDS for independent frequency selection.
* Programmable DDS frequency for all channels.
* Programmable DDS phase offset for all channels.
* Reloadable filter coefficients.
models/*: (2/3) massive dsp changes

* Changed to a Time-division multiplexing approach.
	We are using a 2-multilplexed stream scheme for
	high frequencies (ADC rate) and a 4-multiplexed
	stream scheme for all the other lower rates.

* Oversampling rate of 2 relative to ADC rate.
	Now, a 2xADC rate clock is used for all the
	DSP chain. It allows for a reduced number
	of resources usage at higher rates.

* Fix delta-sigma pre-divider FIFO buffers

* Add 25-bit multipliers for Kx, Ky and Ksum
	(position measurement constants)

* Lower order of BPF at the beggining of the chain,
	in order to reduce the number of FPGA resources
	used (mainly DSP48E1).Also, we are using an
	oversample rate of, so, rougly, 2 times
	less resources are used.

TODO:

* 4-channel DDS for independent frequency selection.
* Programmable DDS frequency for all channels.
* Programmable DDS phase offset for all channels.
* Reloadable filter coefficients.
scripts/*: (3/3) massive dsp changes

 * Changed to a Time-division multiplexing approach.
         We are using a 2-multilplexed stream scheme for
         high frequencies (ADC rate) and a 4-multiplexed
         stream scheme for all the other lower rates.

 * Oversampling rate of 2 relative to ADC rate.
         Now, a 2xADC rate clock is used for all the
          DSP chain. It allows for a reduced number
          of resources usage at higher rates.

  * Fix delta-sigma pre-divider FIFO buffers

  * Add 25-bit multipliers for Kx, Ky and Ksum
          (position measurement constants)

  * Lower order of BPF at the beggining of the chain,
         in order to reduce the number of FPGA resources
          used (mainly DSP48E1).Also, we are using an
          oversample rate of, so, rougly, 2 times
          less resources are used.

TODO:

* 4-channel DDS for independent frequency selection.
* Programmable DDS frequency for all channels.
* Programmable DDS phase offset for all channels.
* Reloadable filter coefficients.
hdl/*: (1/2) Fix all last and ch_out signal delays

The main issue was due to CIC and FIR last signal. We must set
it to one cycle before the actual last TDM data (sysgen bug?)
models/*: (2/2) Fix all last and ch_out signal delays

The main issue was due to CIC and FIR last signal. We must set
it to one cycle before the actual last TDM data (sysgen bug?)
hdl/*/ddc_bpm_476_066_cw.ucf: comment out overconstraints
hdl/*: add xlclockdriver component to package
Merge branch 'devel'