Proper FP rounding for amd64 (VEX part)

This makes rounding mode switches (such as through fesetround()) work
for SSE instructions.  This turns out to be sufficient for some
use-cases, as GCC defaults to SSE instructions on x86_64 except for
'long double'.

The general theme here is:

* We add a new first argument (or replace the fake, in some cases) for
  FP operations: it reads the rounding mode from a register.

* The code generator then turns that argument into a proper rounding
  mode change.  In this patch it does that unconditionally, which is
  slow; we'll fix it later.
Stub rounding mode support for x86 SSE instructions

With the actual rounding support for amd64, some IR instructions had
to change arity and thus the x86 version would no longer work with
them.  Fix these instances.

We make no attempt to actually support rounding here; it simply fills
in a fake rounding mode constant, like the existing code for FPU ops.
Then it ignores that argument when generating code.
Smarter FP rounding (VEX part)

Remember the rounding modes when we set them, and avoid re-setting it to the
same value.  This speeds up FP operations; the idea is stolen from the
PPC rounding mode implementation.
AVX rounding mode support

Follows the theme of the main SSE rounding support patch: add an extra
argument, use it for setting the rounding mode.