Fix so caches properly handle reset.
This was unimplemented after I added global reset.
sram_1r1w does not clear its contents when reset is asserted, which is usually fine.  However, I had put the cache valid bits for the directory and L1 and L2 caches in the same SRAM as the tag bits.  This meant that the valid bits would not be affected by reset and thus there could be random garbage in the caches.
The fix was to break the valid bits into a separate module cache_valid_array, which does have a reset that will clear the contents.
If a RTL assertion is hit during cosimulation, print a meaningful error message.